diff --git a/src/cmd/go.mod b/src/cmd/go.mod
index 4d458ac783b65d331dd5d9ff3d94c871224c9151..89a64e906ea826bb586bc6a61854ddfc90dda4e9 100644
--- a/src/cmd/go.mod
+++ b/src/cmd/go.mod
@@ -4,7 +4,7 @@ go 1.24
require (
github.com/google/pprof v0.0.0-20240722153945-304e4f0156b8
- golang.org/x/arch v0.8.1-0.20240716161256-b863392466ea
+ golang.org/x/arch v0.9.1-0.20240807172201-9d90945922a7
golang.org/x/build v0.0.0-20240722200705-b9910f320300
golang.org/x/mod v0.20.0
golang.org/x/sync v0.8.0
diff --git a/src/cmd/go.sum b/src/cmd/go.sum
index d63f9fec18c36bc98f8ee91be8c679eaeb51da21..c93d286f1289b4da6fbd247c2f7496fd5fdbddf0 100644
--- a/src/cmd/go.sum
+++ b/src/cmd/go.sum
@@ -6,8 +6,8 @@ github.com/ianlancetaylor/demangle v0.0.0-20240312041847-bd984b5ce465 h1:KwWnWVW
github.com/ianlancetaylor/demangle v0.0.0-20240312041847-bd984b5ce465/go.mod h1:gx7rwoVhcfuVKG5uya9Hs3Sxj7EIvldVofAWIUtGouw=
github.com/yuin/goldmark v1.6.0 h1:boZcn2GTjpsynOsC0iJHnBWa4Bi0qzfJjthwauItG68=
github.com/yuin/goldmark v1.6.0/go.mod h1:6yULJ656Px+3vBD8DxQVa3kxgyrAnzto9xy5taEt/CY=
-golang.org/x/arch v0.8.1-0.20240716161256-b863392466ea h1:+dKVGZM+cuxx3fooVKLDxZIPzKR1HYO1Xkd12Je4Z9k=
-golang.org/x/arch v0.8.1-0.20240716161256-b863392466ea/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys=
+golang.org/x/arch v0.9.1-0.20240807172201-9d90945922a7 h1:4+03DsxQb03qtr7e32FA8tiq18ytCUClXaXxQBDRGbs=
+golang.org/x/arch v0.9.1-0.20240807172201-9d90945922a7/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys=
golang.org/x/build v0.0.0-20240722200705-b9910f320300 h1:2Cqg4LnvfD2ZpG8+6KbyYUkweWhNS3SgfcN/eeVseJ0=
golang.org/x/build v0.0.0-20240722200705-b9910f320300/go.mod h1:YsGhg4JUVUWLzdqU2wCrtpRrOveOql6w56FLDHq/CJ4=
golang.org/x/mod v0.20.0 h1:utOm6MM3R3dnawAiJgn0y+xvuYRsm1RKM/4giyfDgV0=
diff --git a/src/cmd/internal/objfile/disasm.go b/src/cmd/internal/objfile/disasm.go
index c298d7e1a93f874c8ab15c4f1416ae3a8c1fc783..960778e8a62f2f8c4a27aec75cda3a1fb3a17021 100644
--- a/src/cmd/internal/objfile/disasm.go
+++ b/src/cmd/internal/objfile/disasm.go
@@ -24,6 +24,7 @@ import (
"golang.org/x/arch/arm/armasm"
"golang.org/x/arch/arm64/arm64asm"
"golang.org/x/arch/ppc64/ppc64asm"
+ "golang.org/x/arch/s390x/s390xasm"
"golang.org/x/arch/x86/x86asm"
)
@@ -383,6 +384,23 @@ func disasm_ppc64(code []byte, pc uint64, lookup lookupFunc, byteOrder binary.By
return text, size
}
+func disasm_s390x(code []byte, pc uint64, lookup lookupFunc, _ binary.ByteOrder, gnuAsm bool) (string, int) {
+ inst, err := s390xasm.Decode(code)
+ var text string
+ size := inst.Len
+ if err != nil || size == 0 || inst.Op == 0 {
+ size = 2
+ text = "?"
+ } else {
+ if gnuAsm {
+ text = fmt.Sprintf("%s", s390xasm.GNUSyntax(inst, pc))
+ } else {
+ text = fmt.Sprintf("%s", "Go/plan9 syntax unsupported..!!")
+ }
+ }
+ return text, size
+}
+
var disasms = map[string]disasmFunc{
"386": disasm_386,
"amd64": disasm_amd64,
@@ -390,6 +408,7 @@ var disasms = map[string]disasmFunc{
"arm64": disasm_arm64,
"ppc64": disasm_ppc64,
"ppc64le": disasm_ppc64,
+ "s390x": disasm_s390x,
}
var byteOrders = map[string]binary.ByteOrder{
diff --git a/src/cmd/objdump/objdump_test.go b/src/cmd/objdump/objdump_test.go
index a755ec3b64400e3a968b1e611d1deb155265545b..ba8c4fbe192343d33f59e6b81f462fac6da27a2f 100644
--- a/src/cmd/objdump/objdump_test.go
+++ b/src/cmd/objdump/objdump_test.go
@@ -104,6 +104,12 @@ var ppcGnuNeed = []string{
"beq",
}
+var s390xGnuNeed = []string{
+ "brasl",
+ "j",
+ "clije",
+}
+
func mustHaveDisasm(t *testing.T) {
switch runtime.GOARCH {
case "loong64":
@@ -112,8 +118,6 @@ func mustHaveDisasm(t *testing.T) {
t.Skipf("skipping on %s, issue 12559", runtime.GOARCH)
case "riscv64":
t.Skipf("skipping on %s, issue 36738", runtime.GOARCH)
- case "s390x":
- t.Skipf("skipping on %s, issue 15255", runtime.GOARCH)
}
}
@@ -202,6 +206,8 @@ func testDisasm(t *testing.T, srcfname string, printCode bool, printGnuAsm bool,
need = append(need, armGnuNeed...)
case "ppc64", "ppc64le":
need = append(need, ppcGnuNeed...)
+ case "s390x":
+ need = append(need, s390xGnuNeed...)
}
}
args = []string{
diff --git a/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/Makefile b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..6d02dac26626612413202a63e12640bced381448
--- /dev/null
+++ b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/Makefile
@@ -0,0 +1,2 @@
+tables.go: ../s390xmap/map.go ../s390x.csv
+ go run ../s390xmap/map.go -fmt=decoder ../s390x.csv >_tables.go && gofmt _tables.go >tables.go && rm _tables.go
diff --git a/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/decode.go b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/decode.go
new file mode 100644
index 0000000000000000000000000000000000000000..823fe5913a926ac650d073aa0178f3322c484b6f
--- /dev/null
+++ b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/decode.go
@@ -0,0 +1,241 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package s390xasm
+
+import (
+ "encoding/binary"
+ "fmt"
+)
+
+// instFormat is a decoding rule for one specific instruction form.
+// An instruction ins matches the rule if ins&Mask == Value.
+// DontCare bits are mainly used for finding the same instruction
+// name differing with the number of argument fields.
+// The Args are stored in the same order as the instruction manual.
+type instFormat struct {
+ Op Op
+ Mask uint64
+ Value uint64
+ DontCare uint64
+ Args [8]*argField
+}
+
+// argField indicate how to decode an argument to an instruction.
+// First parse the value from the BitFields, shift it left by Shift
+// bits to get the actual numerical value.
+type argField struct {
+ Type ArgType
+ flags uint16
+ BitField
+}
+
+// Parse parses the Arg out from the given binary instruction i.
+func (a argField) Parse(i uint64) Arg {
+ switch a.Type {
+ default:
+ return nil
+ case TypeUnknown:
+ return nil
+ case TypeReg:
+ return R0 + Reg(a.BitField.Parse(i))
+ case TypeFPReg:
+ return F0 + Reg(a.BitField.Parse(i))
+ case TypeCReg:
+ return C0 + Reg(a.BitField.Parse(i))
+ case TypeACReg:
+ return A0 + Reg(a.BitField.Parse(i))
+ case TypeBaseReg:
+ return B0 + Base(a.BitField.Parse(i))
+ case TypeIndexReg:
+ return X0 + Index(a.BitField.Parse(i))
+ case TypeDispUnsigned:
+ return Disp12(a.BitField.Parse(i))
+ case TypeDispSigned20:
+ return Disp20(a.BitField.ParseSigned(i))
+ case TypeVecReg:
+ m := i >> 24 // Handling RXB field(bits 36 to 39)
+ if ((m>>3)&0x1 == 1) && (a.BitField.Offs == 8) {
+ return V0 + VReg(a.BitField.Parse(i)) + VReg(16)
+ } else if ((m>>2)&0x1 == 1) && (a.BitField.Offs == 12) {
+ return V0 + VReg(a.BitField.Parse(i)) + VReg(16)
+ } else if ((m>>1)&0x1 == 1) && (a.BitField.Offs == 16) {
+ return V0 + VReg(a.BitField.Parse(i)) + VReg(16)
+ } else if ((m)&0x1 == 1) && (a.BitField.Offs == 32) {
+ return V0 + VReg(a.BitField.Parse(i)) + VReg(16)
+ } else {
+ return V0 + VReg(a.BitField.Parse(i))
+ }
+ case TypeImmSigned8:
+ return Sign8(a.BitField.ParseSigned(i))
+ case TypeImmSigned16:
+ return Sign16(a.BitField.ParseSigned(i))
+ case TypeImmSigned32:
+ return Sign32(a.BitField.ParseSigned(i))
+ case TypeImmUnsigned:
+ return Imm(a.BitField.Parse(i))
+ case TypeRegImSigned12:
+ return RegIm12(a.BitField.ParseSigned(i))
+ case TypeRegImSigned16:
+ return RegIm16(a.BitField.ParseSigned(i))
+ case TypeRegImSigned24:
+ return RegIm24(a.BitField.ParseSigned(i))
+ case TypeRegImSigned32:
+ return RegIm32(a.BitField.ParseSigned(i))
+ case TypeMask:
+ return Mask(a.BitField.Parse(i))
+ case TypeLen:
+ return Len(a.BitField.Parse(i))
+ }
+}
+
+type ArgType int8
+
+const (
+ TypeUnknown ArgType = iota
+ TypeReg // integer register
+ TypeFPReg // floating point register
+ TypeACReg // access register
+ TypeCReg // control register
+ TypeVecReg // vector register
+ TypeImmUnsigned // unsigned immediate/flag/mask, this is the catch-all type
+ TypeImmSigned8 // Signed 8-bit Immdediate
+ TypeImmSigned16 // Signed 16-bit Immdediate
+ TypeImmSigned32 // Signed 32-bit Immdediate
+ TypeBaseReg // Base Register for accessing memory
+ TypeIndexReg // Index Register
+ TypeDispUnsigned // Displacement 12-bit unsigned for memory address
+ TypeDispSigned20 // Displacement 20-bit signed for memory address
+ TypeRegImSigned12 // RegisterImmediate 12-bit signed data
+ TypeRegImSigned16 // RegisterImmediate 16-bit signed data
+ TypeRegImSigned24 // RegisterImmediate 24-bit signed data
+ TypeRegImSigned32 // RegisterImmediate 32-bit signed data
+ TypeMask // 4-bit Mask
+ TypeLen // Length of Memory Operand
+ TypeLast
+)
+
+func (t ArgType) String() string {
+ switch t {
+ default:
+ return fmt.Sprintf("ArgType(%d)", int(t))
+ case TypeUnknown:
+ return "Unknown"
+ case TypeReg:
+ return "Reg"
+ case TypeFPReg:
+ return "FPReg"
+ case TypeACReg:
+ return "ACReg"
+ case TypeCReg:
+ return "CReg"
+ case TypeDispUnsigned:
+ return "DispUnsigned"
+ case TypeDispSigned20:
+ return "DispSigned20"
+ case TypeBaseReg:
+ return "BaseReg"
+ case TypeIndexReg:
+ return "IndexReg"
+ case TypeVecReg:
+ return "VecReg"
+ case TypeImmSigned8:
+ return "ImmSigned8"
+ case TypeImmSigned16:
+ return "ImmSigned16"
+ case TypeImmSigned32:
+ return "ImmSigned32"
+ case TypeImmUnsigned:
+ return "ImmUnsigned"
+ case TypeRegImSigned12:
+ return "RegImSigned12"
+ case TypeRegImSigned16:
+ return "RegImSigned16"
+ case TypeRegImSigned24:
+ return "RegImSigned24"
+ case TypeRegImSigned32:
+ return "RegImSigned32"
+ case TypeMask:
+ return "Mask"
+ case TypeLen:
+ return "Len"
+ }
+}
+
+func (t ArgType) GoString() string {
+ s := t.String()
+ if t > 0 && t < TypeLast {
+ return "Type" + s
+ }
+ return s
+}
+
+var (
+ // Errors
+ errShort = fmt.Errorf("truncated instruction")
+ errUnknown = fmt.Errorf("unknown instruction")
+)
+
+var decoderCover []bool
+
+// Decode decodes the leading bytes in src as a single instruction using
+// byte order ord.
+func Decode(src []byte) (inst Inst, err error) {
+ if len(src) < 2 {
+ return inst, errShort
+ }
+ if decoderCover == nil {
+ decoderCover = make([]bool, len(instFormats))
+ }
+ bit_check := binary.BigEndian.Uint16(src[:2])
+ bit_check = bit_check >> 14
+ l := int(0)
+ if (bit_check & 0x03) == 0 {
+ l = 2
+ } else if bit_check&0x03 == 3 {
+ l = 6
+ } else if (bit_check&0x01 == 1) || (bit_check&0x02 == 2) {
+ l = 4
+ }
+ inst.Len = l
+ ui_extn := uint64(0)
+ switch l {
+ case 2:
+ ui_extn = uint64(binary.BigEndian.Uint16(src[:inst.Len]))
+ inst.Enc = ui_extn
+ ui_extn = ui_extn << 48
+ case 4:
+ ui_extn = uint64(binary.BigEndian.Uint32(src[:inst.Len]))
+ inst.Enc = ui_extn
+ ui_extn = ui_extn << 32
+ case 6:
+ u1 := binary.BigEndian.Uint32(src[:(inst.Len - 2)])
+ u2 := binary.BigEndian.Uint16(src[(inst.Len - 2):inst.Len])
+ ui_extn = uint64(u1)<<16 | uint64(u2)
+ ui_extn = ui_extn << 16
+ inst.Enc = ui_extn
+ default:
+ return inst, errShort
+ }
+ for _, iform := range instFormats {
+ if ui_extn&iform.Mask != iform.Value {
+ continue
+ }
+ if (iform.DontCare & ^(ui_extn)) != iform.DontCare {
+ continue
+ }
+ for j, argfield := range iform.Args {
+ if argfield == nil {
+ break
+ }
+ inst.Args[j] = argfield.Parse(ui_extn)
+ }
+ inst.Op = iform.Op
+ break
+ }
+ if inst.Op == 0 && inst.Enc != 0 {
+ return inst, errUnknown
+ }
+ return inst, nil
+}
diff --git a/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/field.go b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/field.go
new file mode 100644
index 0000000000000000000000000000000000000000..e00415fc094469ce497b0716aecb039c67f767e9
--- /dev/null
+++ b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/field.go
@@ -0,0 +1,98 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package s390xasm
+
+import (
+ "fmt"
+ "strings"
+)
+
+// A BitField is a bit-field in a 64-bit double word.
+// Bits are counted from 0 from the MSB to 63 as the LSB.
+type BitField struct {
+ Offs uint8 // the offset of the left-most bit.
+ Bits uint8 // length in bits.
+}
+
+func (b BitField) String() string {
+ if b.Bits > 1 {
+ return fmt.Sprintf("[%d:%d]", b.Offs, int(b.Offs+b.Bits)-1)
+ } else if b.Bits == 1 {
+ return fmt.Sprintf("[%d]", b.Offs)
+ } else {
+ return fmt.Sprintf("[%d, len=0]", b.Offs)
+ }
+}
+
+// Parse extracts the bitfield b from i, and return it as an unsigned integer.
+// Parse will panic if b is invalid.
+func (b BitField) Parse(i uint64) uint64 {
+ if b.Bits > 64 || b.Bits == 0 || b.Offs > 63 || b.Offs+b.Bits > 64 {
+ panic(fmt.Sprintf("invalid bitfiled %v", b))
+ }
+ if b.Bits == 20 {
+ return ((((i >> (64 - b.Offs - b.Bits)) & ((1 << 8) - 1)) << 12) | ((i >> (64 - b.Offs - b.Bits + 8)) & 0xFFF))
+
+ } else {
+ return (i >> (64 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1)
+ }
+}
+
+// ParseSigned extracts the bitfield b from i, and return it as a signed integer.
+// ParseSigned will panic if b is invalid.
+func (b BitField) ParseSigned(i uint64) int64 {
+ u := int64(b.Parse(i))
+ return u << (64 - b.Bits) >> (64 - b.Bits)
+}
+
+// BitFields is a series of BitFields representing a single number.
+type BitFields []BitField
+
+func (bs BitFields) String() string {
+ ss := make([]string, len(bs))
+ for i, bf := range bs {
+ ss[i] = bf.String()
+ }
+ return fmt.Sprintf("<%s>", strings.Join(ss, "|"))
+}
+
+func (bs *BitFields) Append(b BitField) {
+ *bs = append(*bs, b)
+}
+
+// parse extracts the bitfields from i, concatenate them and return the result
+// as an unsigned integer and the total length of all the bitfields.
+// parse will panic if any bitfield in b is invalid, but it doesn't check if
+// the sequence of bitfields is reasonable.
+func (bs BitFields) parse(i uint64) (u uint64, Bits uint8) {
+ for _, b := range bs {
+ u = (u << b.Bits) | uint64(b.Parse(i))
+ Bits += b.Bits
+ }
+ return u, Bits
+}
+
+// Parse extracts the bitfields from i, concatenate them and return the result
+// as an unsigned integer. Parse will panic if any bitfield in b is invalid.
+func (bs BitFields) Parse(i uint64) uint64 {
+ u, _ := bs.parse(i)
+ return u
+}
+
+// ParseSigned extracts the bitfields from i, concatenate them and return the result
+// as a signed integer. Parse will panic if any bitfield in b is invalid.
+func (bs BitFields) ParseSigned(i uint64) int64 {
+ u, l := bs.parse(i)
+ return int64(u) << (64 - l) >> (64 - l)
+}
+
+// Count the number of bits in the aggregate BitFields
+func (bs BitFields) NumBits() int {
+ num := 0
+ for _, b := range bs {
+ num += int(b.Bits)
+ }
+ return num
+}
diff --git a/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/gnu.go b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/gnu.go
new file mode 100644
index 0000000000000000000000000000000000000000..5755b354e4c3f2faa6da3221f6c4336e85f4c9cf
--- /dev/null
+++ b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/gnu.go
@@ -0,0 +1,1018 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package s390xasm
+
+// Instructions with extended mnemonics fall under various categories.
+// To handle each of them in one single function, various different
+// structure types are defined as below. Corresponding instruction
+// structures are created with the help of these base structures.
+// Different instruction types are as below:
+
+// Typ1 - Instructions having different base and extended mnemonic strings.
+//
+// These instructions have single M-field value and single offset.
+type typ1ExtndMnics struct {
+ BaseOpStr string
+ Value uint8
+ Offset uint8
+ ExtnOpStr string
+}
+
+// Typ2 - Instructions having couple of extra strings added to the base mnemonic string,
+//
+// depending on the condition code evaluation.
+// These instructions have single M-field value and single offset.
+type typ2ExtndMnics struct {
+ Value uint8
+ Offset uint8
+ ExtnOpStr string
+}
+
+// Typ3 - Instructions having couple of extra strings added to the base mnemonic string,
+//
+// depending on the condition code evaluation.
+// These instructions have two M-field values and two offsets.
+type typ3ExtndMnics struct {
+ Value1 uint8
+ Value2 uint8
+ Offset1 uint8
+ Offset2 uint8
+ ExtnOpStr string
+}
+
+// Typ4 - Instructions having different base and extended mnemonic strings.
+//
+// These instructions have two M-field values and two offsets.
+type typ4ExtndMnics struct {
+ BaseOpStr string
+ Value1 uint8
+ Value2 uint8
+ Offset1 uint8
+ Offset2 uint8
+ ExtnOpStr string
+}
+
+// Typ5 - Instructions having different base and extended mnemonic strings.
+//
+// These instructions have three M-field values and three offsets.
+type typ5ExtndMnics struct {
+ BaseOpStr string
+ Value1 uint8
+ Value2 uint8
+ Value3 uint8
+ Offset1 uint8
+ Offset2 uint8
+ Offset3 uint8
+ ExtnOpStr string
+}
+
+// "func Handleextndmnemonic" - This is the function where the extended mnemonic logic
+// is implemented. This function defines various structures to keep a list of base
+// instructions and their extended mnemonic strings. These structure will also have
+// M-field values and offset values defined, based on their type.
+// HandleExtndMnemonic takes "inst" structure as the input variable.
+// Inst structure will have all the details related to an instruction. Based on the
+// opcode base string, a switch-case statement is executed. In that, based on the
+// M-field value and the offset value of that particular M-field, extended mnemonic
+// string is either searched or constructed by adding couple of extra strings to the base
+// opcode string from one of the structure defined below.
+func HandleExtndMnemonic(inst *Inst) string {
+
+ brnchInstrExtndMnics := []typ1ExtndMnics{
+ //BIC - BRANCH INDIRECT ON CONDITION instruction
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 1, Offset: 0, ExtnOpStr: "bio"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 2, Offset: 0, ExtnOpStr: "bih"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 4, Offset: 0, ExtnOpStr: "bil"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 7, Offset: 0, ExtnOpStr: "bine"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 8, Offset: 0, ExtnOpStr: "bie"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 11, Offset: 0, ExtnOpStr: "binl"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 13, Offset: 0, ExtnOpStr: "binh"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 14, Offset: 0, ExtnOpStr: "bino"},
+ typ1ExtndMnics{BaseOpStr: "bic", Value: 15, Offset: 0, ExtnOpStr: "bi"},
+
+ //BCR - BRANCH ON CONDITION instruction
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 0, Offset: 0, ExtnOpStr: "nopr"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 1, Offset: 0, ExtnOpStr: "bor"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 2, Offset: 0, ExtnOpStr: "bhr"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 4, Offset: 0, ExtnOpStr: "blr"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 7, Offset: 0, ExtnOpStr: "bner"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 8, Offset: 0, ExtnOpStr: "ber"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 11, Offset: 0, ExtnOpStr: "bnlr"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 13, Offset: 0, ExtnOpStr: "bnhr"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 14, Offset: 0, ExtnOpStr: "bnor"},
+ typ1ExtndMnics{BaseOpStr: "bcr", Value: 15, Offset: 0, ExtnOpStr: "br"},
+
+ //BC - BRANCH ON CONDITION instruction
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 0, Offset: 0, ExtnOpStr: "nopr"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 1, Offset: 0, ExtnOpStr: "bo"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 2, Offset: 0, ExtnOpStr: "bh"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 4, Offset: 0, ExtnOpStr: "bl"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 7, Offset: 0, ExtnOpStr: "bne"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 8, Offset: 0, ExtnOpStr: "be"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 11, Offset: 0, ExtnOpStr: "bnl"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 13, Offset: 0, ExtnOpStr: "bnh"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 14, Offset: 0, ExtnOpStr: "bno"},
+ typ1ExtndMnics{BaseOpStr: "bc", Value: 15, Offset: 0, ExtnOpStr: "b"},
+
+ //BRC - BRANCH RELATIVE ON CONDITION instruction
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 0, Offset: 0, ExtnOpStr: "jnop"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 1, Offset: 0, ExtnOpStr: "jo"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 2, Offset: 0, ExtnOpStr: "jh"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 4, Offset: 0, ExtnOpStr: "jl"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 7, Offset: 0, ExtnOpStr: "jne"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 8, Offset: 0, ExtnOpStr: "je"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 11, Offset: 0, ExtnOpStr: "jnl"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 13, Offset: 0, ExtnOpStr: "jnh"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 14, Offset: 0, ExtnOpStr: "jno"},
+ typ1ExtndMnics{BaseOpStr: "brc", Value: 15, Offset: 0, ExtnOpStr: "j"},
+
+ //BRCL - BRANCH RELATIVE ON CONDITION LONG instruction
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 0, Offset: 0, ExtnOpStr: "jgnop"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 1, Offset: 0, ExtnOpStr: "jgo"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 2, Offset: 0, ExtnOpStr: "jgh"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 4, Offset: 0, ExtnOpStr: "jgl"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 7, Offset: 0, ExtnOpStr: "jgne"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 8, Offset: 0, ExtnOpStr: "jge"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 11, Offset: 0, ExtnOpStr: "jgnl"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 13, Offset: 0, ExtnOpStr: "jgnh"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 14, Offset: 0, ExtnOpStr: "jgno"},
+ typ1ExtndMnics{BaseOpStr: "brcl", Value: 15, Offset: 0, ExtnOpStr: "jg"},
+ }
+
+ //Compare instructions
+ cmpInstrExtndMnics := []typ2ExtndMnics{
+ typ2ExtndMnics{Value: 2, Offset: 2, ExtnOpStr: "h"},
+ typ2ExtndMnics{Value: 4, Offset: 2, ExtnOpStr: "l"},
+ typ2ExtndMnics{Value: 6, Offset: 2, ExtnOpStr: "ne"},
+ typ2ExtndMnics{Value: 8, Offset: 2, ExtnOpStr: "e"},
+ typ2ExtndMnics{Value: 10, Offset: 2, ExtnOpStr: "nl"},
+ typ2ExtndMnics{Value: 12, Offset: 2, ExtnOpStr: "nh"},
+ }
+
+ //Load and Store instructions
+ ldSt_InstrExtndMnics := []typ2ExtndMnics{
+ typ2ExtndMnics{Value: 1, Offset: 2, ExtnOpStr: "o"},
+ typ2ExtndMnics{Value: 2, Offset: 2, ExtnOpStr: "h"},
+ typ2ExtndMnics{Value: 3, Offset: 2, ExtnOpStr: "nle"},
+ typ2ExtndMnics{Value: 4, Offset: 2, ExtnOpStr: "l"},
+ typ2ExtndMnics{Value: 5, Offset: 2, ExtnOpStr: "nhe"},
+ typ2ExtndMnics{Value: 6, Offset: 2, ExtnOpStr: "lh"},
+ typ2ExtndMnics{Value: 7, Offset: 2, ExtnOpStr: "ne"},
+ typ2ExtndMnics{Value: 8, Offset: 2, ExtnOpStr: "e"},
+ typ2ExtndMnics{Value: 9, Offset: 2, ExtnOpStr: "nlh"},
+ typ2ExtndMnics{Value: 10, Offset: 2, ExtnOpStr: "he"},
+ typ2ExtndMnics{Value: 11, Offset: 2, ExtnOpStr: "nl"},
+ typ2ExtndMnics{Value: 12, Offset: 2, ExtnOpStr: "le"},
+ typ2ExtndMnics{Value: 13, Offset: 2, ExtnOpStr: "nh"},
+ typ2ExtndMnics{Value: 14, Offset: 2, ExtnOpStr: "no"},
+ }
+
+ vecInstrExtndMnics := []typ2ExtndMnics{
+ typ2ExtndMnics{Value: 0, Offset: 3, ExtnOpStr: "b"},
+ typ2ExtndMnics{Value: 1, Offset: 3, ExtnOpStr: "h"},
+ typ2ExtndMnics{Value: 2, Offset: 3, ExtnOpStr: "f"},
+ typ2ExtndMnics{Value: 3, Offset: 3, ExtnOpStr: "g"},
+ typ2ExtndMnics{Value: 4, Offset: 3, ExtnOpStr: "q"},
+ typ2ExtndMnics{Value: 6, Offset: 3, ExtnOpStr: "lf"},
+ }
+
+ //VCEQ, VCH, VCHL
+ vec2InstrExtndMnics := []typ3ExtndMnics{
+ typ3ExtndMnics{Value1: 0, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "b"},
+ typ3ExtndMnics{Value1: 1, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "h"},
+ typ3ExtndMnics{Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "f"},
+ typ3ExtndMnics{Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "g"},
+ typ3ExtndMnics{Value1: 0, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "bs"},
+ typ3ExtndMnics{Value1: 1, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "hs"},
+ typ3ExtndMnics{Value1: 2, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "fs"},
+ typ3ExtndMnics{Value1: 3, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "gs"},
+ }
+
+ //VFAE, VFEE, VFENE
+ vec21InstrExtndMnics := []typ3ExtndMnics{
+ typ3ExtndMnics{Value1: 0, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "b"},
+ typ3ExtndMnics{Value1: 1, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "h"},
+ typ3ExtndMnics{Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "f"},
+ typ3ExtndMnics{Value1: 0, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "bs"},
+ typ3ExtndMnics{Value1: 1, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "hs"},
+ typ3ExtndMnics{Value1: 2, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "fs"},
+ typ3ExtndMnics{Value1: 0, Value2: 2, Offset1: 3, Offset2: 4, ExtnOpStr: "zb"},
+ typ3ExtndMnics{Value1: 1, Value2: 2, Offset1: 3, Offset2: 4, ExtnOpStr: "zh"},
+ typ3ExtndMnics{Value1: 2, Value2: 2, Offset1: 3, Offset2: 4, ExtnOpStr: "zf"},
+ typ3ExtndMnics{Value1: 0, Value2: 3, Offset1: 3, Offset2: 4, ExtnOpStr: "zbs"},
+ typ3ExtndMnics{Value1: 1, Value2: 3, Offset1: 3, Offset2: 4, ExtnOpStr: "zhs"},
+ typ3ExtndMnics{Value1: 2, Value2: 3, Offset1: 3, Offset2: 4, ExtnOpStr: "zfs"},
+ }
+
+ vec3InstrExtndMnics := []typ3ExtndMnics{
+ typ3ExtndMnics{Value1: 2, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "sb"},
+ typ3ExtndMnics{Value1: 3, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "db"},
+ typ3ExtndMnics{Value1: 4, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "xb"},
+ }
+
+ vec4InstrExtndMnics := []typ4ExtndMnics{
+ // VFA - VECTOR FP ADD
+ typ4ExtndMnics{BaseOpStr: "vfa", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfasb"},
+ typ4ExtndMnics{BaseOpStr: "vfa", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfadb"},
+ typ4ExtndMnics{BaseOpStr: "vfa", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfasb"},
+ typ4ExtndMnics{BaseOpStr: "vfa", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfadb"},
+ typ4ExtndMnics{BaseOpStr: "vfa", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfaxb"},
+
+ // VFD - VECTOR FP DIVIDE
+ typ4ExtndMnics{BaseOpStr: "vfd", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfdsb"},
+ typ4ExtndMnics{BaseOpStr: "vfd", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfddb"},
+ typ4ExtndMnics{BaseOpStr: "vfd", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfdsb"},
+ typ4ExtndMnics{BaseOpStr: "vfd", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfddb"},
+ typ4ExtndMnics{BaseOpStr: "vfd", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfdxb"},
+
+ // VFLL - VECTOR FP LOAD LENGTHENED
+ typ4ExtndMnics{BaseOpStr: "vfll", Value1: 2, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "vflfs"},
+ typ4ExtndMnics{BaseOpStr: "vfll", Value1: 2, Value2: 8, Offset1: 2, Offset2: 3, ExtnOpStr: "wflls"},
+ typ4ExtndMnics{BaseOpStr: "vfll", Value1: 3, Value2: 8, Offset1: 2, Offset2: 3, ExtnOpStr: "wflld"},
+
+ // VFMAX - VECTOR FP MAXIMUM
+ typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmaxsb"},
+ typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmaxdb"},
+ typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmaxsb"},
+ typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmaxdb"},
+ typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmaxxb"},
+
+ // VFMIN - VECTOR FP MINIMUM
+ typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfminsb"},
+ typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmindb"},
+ typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfminsb"},
+ typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmindb"},
+ typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfminxb"},
+
+ // VFM - VECTOR FP MULTIPLY
+ typ4ExtndMnics{BaseOpStr: "vfm", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmsb"},
+ typ4ExtndMnics{BaseOpStr: "vfm", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmdb"},
+ typ4ExtndMnics{BaseOpStr: "vfm", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmsb"},
+ typ4ExtndMnics{BaseOpStr: "vfm", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmdb"},
+ typ4ExtndMnics{BaseOpStr: "vfm", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmxb"},
+
+ // VFSQ - VECTOR FP SQUARE ROOT
+ typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfsqsb"},
+ typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfsqdb"},
+ typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsqsb"},
+ typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsqdb"},
+ typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsqxb"},
+
+ // VFS - VECTOR FP SUBTRACT
+ typ4ExtndMnics{BaseOpStr: "vfs", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfssb"},
+ typ4ExtndMnics{BaseOpStr: "vfs", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfsdb"},
+ typ4ExtndMnics{BaseOpStr: "vfs", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfssb"},
+ typ4ExtndMnics{BaseOpStr: "vfs", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsdb"},
+ typ4ExtndMnics{BaseOpStr: "vfs", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsxb"},
+
+ // VFTCI - VECTOR FP TEST DATA CLASS IMMEDIATE
+ typ4ExtndMnics{BaseOpStr: "vftci", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vftcisb"},
+ typ4ExtndMnics{BaseOpStr: "vftci", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vftcidb"},
+ typ4ExtndMnics{BaseOpStr: "vftci", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wftcisb"},
+ typ4ExtndMnics{BaseOpStr: "vftci", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wftcidb"},
+ typ4ExtndMnics{BaseOpStr: "vftci", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wftcixb"},
+ }
+
+ vec6InstrExtndMnics := []typ5ExtndMnics{
+ // VFCE - VECTOR FP COMPARE EQUAL
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcesb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcedb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcesb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcedb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcedbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcexb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcexbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkesb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkedb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkedbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkesb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkedb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkedbs"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkexb"},
+ typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkexbs"},
+
+ // VFCH - VECTOR FP COMPARE HIGH
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchsb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchsbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchdb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchdbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchsb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchsbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchdb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchdbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchxb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchxbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhsb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhsbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhdb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhdbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhsb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhsbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhdb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhdbs"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhxb"},
+ typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhxbs"},
+
+ // VFCHE - VECTOR FP COMPARE HIGH OR EQUAL
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchesb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchedb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchedbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchesb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchedb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchedbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchexb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchexbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhesb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhedb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhedbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhesb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhesbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhedb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhedbs"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhexb"},
+ typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhexbs"},
+
+ // VFPSO - VECTOR FP PERFORM SIGN OPERATION
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 0, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflcsb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 8, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflcsb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 0, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflnsb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 8, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflnsb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 0, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflpsb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 8, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflpsb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 0, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflcdb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 8, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflcdb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 0, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflndb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 8, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflndb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 0, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflpdb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 8, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflpdb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 4, Value2: 8, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflcxb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 4, Value2: 8, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflnxb"},
+ typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 4, Value2: 8, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflpxb"},
+ }
+
+ vec7InstrExtndMnics := []typ4ExtndMnics{
+ // VFMA - VECTOR FP MULTIPLY AND ADD
+ typ4ExtndMnics{BaseOpStr: "vfma", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmasb"},
+ typ4ExtndMnics{BaseOpStr: "vfma", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmadb"},
+ typ4ExtndMnics{BaseOpStr: "vfma", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmasb"},
+ typ4ExtndMnics{BaseOpStr: "vfma", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmadb"},
+ typ4ExtndMnics{BaseOpStr: "vfma", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmaxb"},
+
+ // VFMS - VECTOR FP MULTIPLY AND SUBTRACT
+ typ4ExtndMnics{BaseOpStr: "vfms", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmssb"},
+ typ4ExtndMnics{BaseOpStr: "vfms", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmsdb"},
+ typ4ExtndMnics{BaseOpStr: "vfms", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmssb"},
+ typ4ExtndMnics{BaseOpStr: "vfms", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmsdb"},
+ typ4ExtndMnics{BaseOpStr: "vfms", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmsxb"},
+
+ // VFNMA - VECTOR FP NEGATIVE MULTIPLY AND ADD
+ typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmasb"},
+ typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmadb"},
+ typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmasb"},
+ typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmadb"},
+ typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmaxb"},
+
+ // VFNMS - VECTOR FP NEGATIVE MULTIPLY AND SUBTRACT
+ typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmssb"},
+ typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmsdb"},
+ typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmssb"},
+ typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmsdb"},
+ typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmsxb"},
+ }
+
+ opString := inst.Op.String()
+ newOpStr := opString
+
+ if inst.Enc == 0 {
+ return ".long 0x0"
+ } else if inst.Op == 0 {
+ return "error: unknown instruction"
+ }
+
+ switch opString {
+ // Case to handle all "branch" instructions with one M-field operand
+ case "bic", "bcr", "bc", "brc", "brcl":
+
+ for i := 0; i < len(brnchInstrExtndMnics); i++ {
+ if opString == brnchInstrExtndMnics[i].BaseOpStr &&
+ uint8(inst.Args[brnchInstrExtndMnics[i].Offset].(Mask)) == brnchInstrExtndMnics[i].Value {
+ newOpStr = brnchInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(brnchInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+
+ // Case to handle all "compare" instructions with one M-field operand
+ case "crb", "cgrb", "crj", "cgrj", "crt", "cgrt", "cib", "cgib", "cij", "cgij", "cit", "cgit", "clrb", "clgrb",
+ "clrj", "clgrj", "clrt", "clgrt", "clt", "clgt", "clib", "clgib", "clij", "clgij", "clfit", "clgit":
+
+ for i := 0; i < len(cmpInstrExtndMnics); i++ {
+ //For CLT and CLGT instructions, M-value is the second operand.
+ //Hence, set the offset to "1"
+ if opString == "clt" || opString == "clgt" {
+ cmpInstrExtndMnics[i].Offset = 1
+ }
+
+ if uint8(inst.Args[cmpInstrExtndMnics[i].Offset].(Mask)) == cmpInstrExtndMnics[i].Value {
+ newOpStr = opString + cmpInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(cmpInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+
+ // Case to handle all "load" and "store" instructions with one M-field operand
+ case "lochhi", "lochi", "locghi", "locfhr", "locfh", "locr", "locgr", "loc",
+ "locg", "selr", "selgr", "selfhr", "stocfh", "stoc", "stocg":
+
+ for i := 0; i < len(ldSt_InstrExtndMnics); i++ {
+
+ //For LOCFH, LOC, LOCG, SELR, SELGR, SELFHR, STOCFH, STOC, STOCG instructions,
+ //M-value is the forth operand. Hence, set the offset to "3"
+ if opString == "locfh" || opString == "loc" || opString == "locg" || opString == "selr" || opString == "selgr" ||
+ opString == "selfhr" || opString == "stocfh" || opString == "stoc" || opString == "stocg" {
+ ldSt_InstrExtndMnics[i].Offset = 3
+ }
+
+ if uint8(inst.Args[ldSt_InstrExtndMnics[i].Offset].(Mask)) == ldSt_InstrExtndMnics[i].Value {
+ newOpStr = opString + ldSt_InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(ldSt_InstrExtndMnics[i].Offset))
+ break
+ }
+ }
+
+ // Case to handle all "vector" instructions with one M-field operand
+ case "vavg", "vavgl", "verllv", "veslv", "vesrav", "vesrlv", "vgfm", "vgm", "vmx", "vmxl", "vmrh", "vmrl", "vmn", "vmnl", "vrep",
+ "vclz", "vctz", "vec", "vecl", "vlc", "vlp", "vpopct", "vrepi", "verim", "verll", "vesl", "vesra", "vesrl", "vgfma", "vlrep",
+ "vlgv", "vlvg", "vlbrrep", "vler", "vlbr", "vstbr", "vster", "vpk", "vme", "vmh", "vmle", "vmlh", "vmlo", "vml", "vmo", "vmae",
+ "vmale", "vmalo", "vmal", "vmah", "vmalh", "vmao", "vmph", "vmplh", "vupl", "vupll", "vscbi", "vs", "vsum", "vsumg", "vsumq",
+ "va", "vacc":
+
+ switch opString {
+
+ case "vavg", "vavgl", "verllv", "veslv", "vesrav", "vesrlv", "vgfm", "vgm", "vmx", "vmxl", "vmrh", "vmrl", "vmn", "vmnl", "vrep":
+ //M-field is 3rd arg for all these instructions. Hence, set the offset to "2"
+ for i := 0; i < len(vecInstrExtndMnics)-2; i++ { // 0,1,2,3
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+
+ case "vclz", "vctz", "vec", "vecl", "vlc", "vlp", "vpopct", "vrepi":
+ for i := 0; i < len(vecInstrExtndMnics)-2; i++ { //0,1,2,3
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset-1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset-1))
+ break
+ }
+ }
+
+ case "verim", "verll", "vesl", "vesra", "vesrl", "vgfma", "vlrep":
+ for i := 0; i < len(vecInstrExtndMnics)-2; i++ { //0,1,2,3
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1))
+ break
+ }
+ }
+
+ case "vlgv", "vlvg":
+ for i := 0; i < len(vecInstrExtndMnics)-2; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1))
+ break
+ }
+ }
+
+ case "vlbrrep", "vler", "vster":
+ for i := 1; i < len(vecInstrExtndMnics)-2; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1))
+ break
+ }
+ }
+
+ case "vpk":
+ for i := 1; i < len(vecInstrExtndMnics)-2; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+
+ case "vlbr", "vstbr":
+ for i := 1; i < len(vecInstrExtndMnics)-1; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1))
+ break
+ }
+ }
+ case "vme", "vmh", "vmle", "vmlh", "vmlo", "vmo":
+ for i := 0; i < len(vecInstrExtndMnics)-3; i++ { //0,1,2
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+
+ case "vml":
+ for i := 0; i < len(vecInstrExtndMnics)-3; i++ { //0,1,2
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == 1 {
+ newOpStr = opString + string("hw")
+ } else {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ }
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+
+ case "vmae", "vmale", "vmalo", "vmal", "vmah", "vmalh", "vmao":
+ for i := 0; i < len(vecInstrExtndMnics)-3; i++ { //0,1,2
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1))
+ break
+ }
+ }
+
+ case "vmph", "vmplh", "vupl", "vupll": //0,1,2
+ for i := 0; i < len(vecInstrExtndMnics)-3; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset-1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset-1))
+ break
+ }
+ }
+
+ case "vscbi", "vs", "va", "vacc": // 0,1,2,3,4
+ for i := 0; i < len(vecInstrExtndMnics)-1; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+ case "vsum", "vsumg":
+ for i := 1; i < len(vecInstrExtndMnics)-4; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+ case "vsumq":
+ for i := 2; i < len(vecInstrExtndMnics)-2; i++ {
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
+ break
+ }
+ }
+ }
+
+ case "vllez":
+ for i := 0; i < len(vecInstrExtndMnics); i++ {
+ if i == 4 {
+ continue
+ }
+ if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value {
+ newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1))
+ break
+ }
+ }
+
+ case "vgbm":
+ if uint16(inst.Args[1].(Imm)) == uint16(0) {
+ newOpStr = "vzeo"
+ removeArg(inst, int8(1))
+ } else if uint16(inst.Args[1].(Imm)) == uint16(0xFFFF) {
+ newOpStr = "vone"
+ removeArg(inst, int8(1))
+ }
+ case "vno":
+ if uint8(inst.Args[1].(VReg)) == uint8(inst.Args[2].(VReg)) { //Bitwise Not instruction(VNOT) if V2 equal to v3
+ newOpStr = opString + "t"
+ removeArg(inst, int8(2))
+ }
+
+ case "vmsl":
+ if uint8(inst.Args[4].(Mask)) == uint8(3) {
+ newOpStr = opString + "g"
+ removeArg(inst, int8(4))
+ }
+
+ case "vflr":
+ if uint8(inst.Args[2].(Mask)) == uint8(3) && ((inst.Args[3].(Mask)>>3)&0x1 == 0x1) {
+ inst.Args[3] = (inst.Args[3].(Mask) ^ 0x8)
+ newOpStr = "wflrd"
+ removeArg(inst, int8(2))
+ } else if uint8(inst.Args[2].(Mask)) == uint8(4) && ((inst.Args[3].(Mask)>>3)&0x1 == 0x1) {
+ inst.Args[3] = (inst.Args[3].(Mask) ^ 0x8)
+ newOpStr = "wflrx"
+ removeArg(inst, int8(2))
+ } else if uint8(inst.Args[2].(Mask)) == uint8(3) {
+ newOpStr = "vflrd"
+ removeArg(inst, int8(2))
+ }
+
+ case "vllebrz":
+ if uint8(inst.Args[4].(Mask)) == uint8(1) {
+ newOpStr = opString + "h"
+ removeArg(inst, int8(4))
+ } else if uint8(inst.Args[4].(Mask)) == uint8(2) {
+ newOpStr = opString + "f"
+ removeArg(inst, int8(4))
+ } else if uint8(inst.Args[4].(Mask)) == uint8(3) {
+ newOpStr = "ldrv"
+ removeArg(inst, int8(4))
+ } else if uint8(inst.Args[4].(Mask)) == uint8(6) {
+ newOpStr = "lerv"
+ removeArg(inst, int8(4))
+ }
+
+ case "vschp":
+ if uint8(inst.Args[3].(Mask)) == uint8(2) {
+ newOpStr = "vschsp"
+ removeArg(inst, int8(3))
+ } else if uint8(inst.Args[3].(Mask)) == uint8(3) {
+ newOpStr = "vschdp"
+ removeArg(inst, int8(3))
+ } else if uint8(inst.Args[3].(Mask)) == uint8(4) {
+ newOpStr = "vschxp"
+ removeArg(inst, int8(3))
+ }
+
+ case "vsbcbi", "vsbi":
+ if uint8(inst.Args[4].(Mask)) == uint8(4) {
+ newOpStr = opString + vecInstrExtndMnics[4].ExtnOpStr
+ removeArg(inst, int8(4))
+ }
+
+ case "vac", "vaccc":
+ if uint8(inst.Args[4].(Mask)) == uint8(4) {
+ newOpStr = opString + vecInstrExtndMnics[3].ExtnOpStr
+ removeArg(inst, int8(3))
+ }
+
+ case "vceq", "vch", "vchl":
+ for i := 0; i < len(vec2InstrExtndMnics)-6; i++ {
+ if uint8(inst.Args[vec2InstrExtndMnics[i].Offset1].(Mask)) == vec2InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec2InstrExtndMnics[i].Offset2].(Mask)) == vec2InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec2InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec2InstrExtndMnics[i].Offset1))
+ removeArg(inst, int8(vec2InstrExtndMnics[i].Offset2-1))
+ break
+ }
+ }
+
+ case "vpks", "vpkls":
+ for i := 1; i < len(vec2InstrExtndMnics)-6; i++ {
+ if i == 4 {
+ continue
+ }
+ if uint8(inst.Args[vec2InstrExtndMnics[i].Offset1].(Mask)) == vec2InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec2InstrExtndMnics[i].Offset2].(Mask)) == vec2InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec2InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec2InstrExtndMnics[i].Offset1))
+ removeArg(inst, int8(vec2InstrExtndMnics[i].Offset2-1))
+ break
+ }
+ }
+ case "vfee", "vfene":
+ var check bool
+ for i := 0; i < len(vec21InstrExtndMnics); i++ {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2].(Mask)) == vec21InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1))
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2-1))
+ check = true
+ break
+ }
+ }
+ if !check {
+ if uint8(inst.Args[3].(Mask)) == 0 && (uint8(inst.Args[4].(Mask)) != uint8(0)) {
+ newOpStr = opString + vec21InstrExtndMnics[0].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[0].Offset1))
+ } else if uint8(inst.Args[3].(Mask)) == 1 && (uint8(inst.Args[4].(Mask)) != uint8(0)) {
+ newOpStr = opString + vec21InstrExtndMnics[1].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[1].Offset1))
+ } else if uint8(inst.Args[3].(Mask)) == 2 && (uint8(inst.Args[4].(Mask)) != uint8(0)) {
+ newOpStr = opString + vec21InstrExtndMnics[2].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[2].Offset1))
+ } else if uint8(inst.Args[4].(Mask)) == 0 {
+ removeArg(inst, int8(vec21InstrExtndMnics[2].Offset2))
+ }
+ }
+
+ case "vfae", "vstrc":
+ off := uint8(0)
+ var check bool
+ if opString == "vstrc" {
+ off = uint8(1)
+ }
+ for i := 0; i < len(vec21InstrExtndMnics)-9; i++ {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+off].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask)) == vec21InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off))
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2+off-1))
+ check = true
+ break
+ }
+ }
+
+ for i := 0; !(check) && (i < len(vec21InstrExtndMnics)-9); i++ {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+off].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask)) == vec21InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off))
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2+off-1))
+ check = true
+ break
+ }
+ }
+ //for i := 3; !(check) && (i < len(vec21InstrExtndMnics)); i++ {
+ for i := len(vec21InstrExtndMnics) - 1; !(check) && (i > 2); i-- {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+off].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask))&(vec21InstrExtndMnics[i].Value2) == vec21InstrExtndMnics[i].Value2 {
+ x := uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask)) ^ (vec21InstrExtndMnics[i].Value2)
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ if x != 0 {
+ inst.Args[vec21InstrExtndMnics[i].Offset2+off] = Mask(x)
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off))
+ check = true
+ break
+ } else {
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off))
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2+off-1))
+ check = true
+ break
+ }
+ }
+ }
+ if !check && inst.Args[4+off].(Mask) == Mask(0) {
+ removeArg(inst, int8(4+off))
+ break
+ }
+
+ case "vstrs":
+ var check bool
+ for i := 0; i < len(vec21InstrExtndMnics)-3; i++ {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+1].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+1].(Mask)) == vec21InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+1))
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2))
+ check = true
+ break
+ }
+ if i == 2 {
+ i = i + 3
+ }
+ }
+
+ for i := 0; !(check) && (i < len(vec21InstrExtndMnics)-9); i++ {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+1].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+1].(Mask)) != 0 {
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+1))
+ break
+ }
+ }
+
+ case "vistr":
+ var check bool
+ for i := 0; i < len(vec21InstrExtndMnics)-6; i++ {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1-1].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2-1].(Mask)) == vec21InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1-1))
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2-2))
+ check = true
+ break
+ }
+ }
+
+ for i := 0; !(check) && (i < len(vec21InstrExtndMnics)-9); i++ {
+ if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1-1].(Mask)) == vec21InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec21InstrExtndMnics[i].Offset2-1].(Mask)) != 0 {
+ newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1-1))
+ break
+ }
+ }
+
+ if uint8(inst.Args[3].(Mask)) == 0 {
+ removeArg(inst, int8(3))
+ break
+ }
+
+ case "vcfps":
+ if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wcefb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wcdgb"
+ removeArg(inst, int8(2))
+ break
+ } else if uint8(inst.Args[2].(Mask)) == uint8(2) {
+ newOpStr = "vcefb"
+ removeArg(inst, int8(2))
+ break
+ } else if uint8(inst.Args[2].(Mask)) == uint8(3) {
+ newOpStr = "vcdgb"
+ removeArg(inst, int8(2))
+ break
+ }
+
+ case "vcfpl":
+ if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wcelfb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wcdlgb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(2) {
+ newOpStr = "vcelfb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) {
+ newOpStr = "vcdlgb"
+ removeArg(inst, int8(2))
+ break
+ }
+
+ case "vcsfp":
+ if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wcfeb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wcgdb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(2) {
+ newOpStr = "vcfeb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) {
+ newOpStr = "vcgdb"
+ removeArg(inst, int8(2))
+ break
+ }
+
+ case "vclfp":
+ if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wclfeb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8))
+ newOpStr = "wclgdb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(2) {
+ newOpStr = "vclfeb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) {
+ newOpStr = "vclgdb"
+ removeArg(inst, int8(2))
+ break
+ }
+
+ case "vfi":
+ if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ newOpStr = "wfisb"
+ removeArg(inst, int8(2))
+ inst.Args[2] = Mask((inst.Args[2].(Mask)) ^ (0x8))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x3) == 1) {
+ newOpStr = "wfidb"
+ removeArg(inst, int8(2))
+ inst.Args[2] = Mask((inst.Args[2].(Mask)) ^ (0x8))
+ break
+ } else if inst.Args[2].(Mask) == Mask(4) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) {
+ newOpStr = "wfixb"
+ removeArg(inst, int8(2))
+ inst.Args[2] = Mask((inst.Args[2].(Mask)) ^ (0x8))
+ break
+ } else if inst.Args[2].(Mask) == Mask(2) {
+ newOpStr = "vfisb"
+ removeArg(inst, int8(2))
+ break
+ } else if inst.Args[2].(Mask) == Mask(3) {
+ newOpStr = "vfidb"
+ removeArg(inst, int8(2))
+ break
+ }
+
+ // Case to handle few vector instructions with 2 M-field operands
+ case "vfa", "vfd", "vfll", "vfmax", "vfmin", "vfm":
+ for i := 0; i < len(vec4InstrExtndMnics); i++ {
+ if opString == vec4InstrExtndMnics[i].BaseOpStr &&
+ uint8(inst.Args[vec4InstrExtndMnics[i].Offset1].(Mask)) == vec4InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec4InstrExtndMnics[i].Offset2].(Mask)) == vec4InstrExtndMnics[i].Value2 {
+ newOpStr = vec4InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec4InstrExtndMnics[i].Offset1))
+ removeArg(inst, int8(vec4InstrExtndMnics[i].Offset2-1))
+ break
+ }
+ }
+
+ // Case to handle few special "vector" instructions with 2 M-field operands
+ case "wfc", "wfk":
+ for i := 0; i < len(vec3InstrExtndMnics); i++ {
+ if uint8(inst.Args[vec3InstrExtndMnics[i].Offset1].(Mask)) == vec3InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec3InstrExtndMnics[i].Offset2].(Mask)) == vec3InstrExtndMnics[i].Value2 {
+ newOpStr = opString + vec3InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec3InstrExtndMnics[i].Offset1))
+ removeArg(inst, int8(vec3InstrExtndMnics[i].Offset2-1))
+ break
+ }
+ }
+
+ // Case to handle few vector instructions with 2 M-field operands
+ case "vfma", "vfms", "vfnma", "vfnms":
+ for i := 0; i < len(vec7InstrExtndMnics); i++ {
+ if opString == vec7InstrExtndMnics[i].BaseOpStr &&
+ uint8(inst.Args[vec7InstrExtndMnics[i].Offset1].(Mask)) == vec7InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec7InstrExtndMnics[i].Offset2].(Mask)) == vec7InstrExtndMnics[i].Value2 {
+ newOpStr = vec7InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec7InstrExtndMnics[i].Offset1))
+ removeArg(inst, int8(vec7InstrExtndMnics[i].Offset2-1))
+ break
+ }
+ }
+
+ // List of instructions with 3 M-field operands.
+ case "vfce", "vfch", "vfche", "vfpso":
+ for i := 0; i < len(vec6InstrExtndMnics); i++ {
+ if opString == vec6InstrExtndMnics[i].BaseOpStr &&
+ uint8(inst.Args[vec6InstrExtndMnics[i].Offset1].(Mask)) == vec6InstrExtndMnics[i].Value1 &&
+ uint8(inst.Args[vec6InstrExtndMnics[i].Offset2].(Mask)) == vec6InstrExtndMnics[i].Value2 &&
+ uint8(inst.Args[vec6InstrExtndMnics[i].Offset3].(Mask)) == vec6InstrExtndMnics[i].Value3 {
+ newOpStr = vec6InstrExtndMnics[i].ExtnOpStr
+ removeArg(inst, int8(vec6InstrExtndMnics[i].Offset1))
+ removeArg(inst, int8(vec6InstrExtndMnics[i].Offset2-1))
+ removeArg(inst, int8(vec6InstrExtndMnics[i].Offset3-2))
+ break
+ }
+ }
+
+ default:
+ return opString
+ }
+ return newOpStr
+}
+
+// This is the function that is called to print the disassembled instruction
+// in the GNU (AT&T) syntax form.
+func GNUSyntax(inst Inst, pc uint64) string {
+ if inst.Enc == 0 {
+ return ".long 0x0"
+ } else if inst.Op == 0 {
+ return "error: unknown instruction"
+ }
+ return inst.String(pc)
+}
+
+// removeArg removes the arg in inst.Args[index].
+func removeArg(inst *Inst, index int8) {
+ for i := int(index); i < len(inst.Args); i++ {
+ if i+1 < len(inst.Args) {
+ inst.Args[i] = inst.Args[i+1]
+ } else {
+ inst.Args[i] = nil
+ }
+ }
+}
diff --git a/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/inst.go b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/inst.go
new file mode 100644
index 0000000000000000000000000000000000000000..19d70156e38530f2165a5cd4d924cbe805152fab
--- /dev/null
+++ b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/inst.go
@@ -0,0 +1,399 @@
+// Copyright 2024 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package s390xasm
+
+import (
+ "bytes"
+ "fmt"
+ "strings"
+)
+
+type Inst struct {
+ Op Op // Opcode mnemonic
+ Enc uint64 // Raw encoding bits (if Len == 8, this is the prefix word)
+ Len int // Length of encoding in bytes.
+ Args Args // Instruction arguments, in Power ISA manual order.
+}
+
+func (i Inst) String(pc uint64) string {
+ var buf bytes.Buffer
+ var rxb_check bool
+ m := i.Op.String()
+ if strings.HasPrefix(m, "v") || strings.Contains(m, "wfc") || strings.Contains(m, "wfk") {
+ rxb_check = true
+ }
+ mnemonic := HandleExtndMnemonic(&i)
+ buf.WriteString(fmt.Sprintf("%s", mnemonic))
+ for j, arg := range i.Args {
+ if arg == nil {
+ break
+ }
+ if j == 0 {
+ buf.WriteString(" ")
+ } else {
+ switch arg.(type) {
+ case VReg, Reg:
+ if _, ok := i.Args[j-1].(Disp12); ok {
+ buf.WriteString("")
+ } else if _, ok := i.Args[j-1].(Disp20); ok {
+ buf.WriteString("")
+ } else {
+ buf.WriteString(",")
+ }
+ case Base:
+ if _, ok := i.Args[j-1].(VReg); ok {
+ buf.WriteString(",")
+ } else if _, ok := i.Args[j-1].(Reg); ok {
+ buf.WriteString(",")
+ }
+ case Index, Len:
+ default:
+ buf.WriteString(",")
+ }
+ }
+ buf.WriteString(arg.String(pc))
+ if rxb_check && i.Args[j+2] == nil {
+ break
+ }
+ }
+ return buf.String()
+}
+
+// An Op is an instruction operation.
+type Op uint16
+
+func (o Op) String() string {
+ if int(o) >= len(opstr) || opstr[o] == "" {
+ return fmt.Sprintf("Op(%d)", int(o))
+ }
+ return opstr[o]
+}
+
+// An Arg is a single instruction argument.
+// One of these types: Reg, Base, Index, Disp20, Disp12, Len, Mask, Sign8, Sign16, Sign32, RegIm12, RegIm16, RegIm24, RegIm32.
+type Arg interface {
+ IsArg()
+ String(pc uint64) string
+}
+
+// An Args holds the instruction arguments.
+// If an instruction has fewer than 6 arguments,
+// the final elements in the array are nil.
+type Args [8]Arg
+
+// Base represents an 4-bit Base Register field
+type Base uint8
+
+const (
+ B0 Base = iota
+ B1
+ B2
+ B3
+ B4
+ B5
+ B6
+ B7
+ B8
+ B9
+ B10
+ B11
+ B12
+ B13
+ B14
+ B15
+)
+
+func (Base) IsArg() {}
+func (r Base) String(pc uint64) string {
+ switch {
+ case B1 <= r && r <= B15:
+ s := "%"
+ return fmt.Sprintf("%sr%d)", s, int(r-B0))
+ case B0 == r:
+ return fmt.Sprintf("")
+ default:
+ return fmt.Sprintf("Base(%d)", int(r))
+ }
+}
+
+// Index represents an 4-bit Index Register field
+type Index uint8
+
+const (
+ X0 Index = iota
+ X1
+ X2
+ X3
+ X4
+ X5
+ X6
+ X7
+ X8
+ X9
+ X10
+ X11
+ X12
+ X13
+ X14
+ X15
+)
+
+func (Index) IsArg() {}
+func (r Index) String(pc uint64) string {
+ switch {
+ case X1 <= r && r <= X15:
+ s := "%"
+ return fmt.Sprintf("%sr%d,", s, int(r-X0))
+ case X0 == r:
+ return fmt.Sprintf("")
+ default:
+ return fmt.Sprintf("Base(%d)", int(r))
+ }
+}
+
+// Disp20 represents an 20-bit Unsigned Displacement
+type Disp20 uint32
+
+func (Disp20) IsArg() {}
+func (r Disp20) String(pc uint64) string {
+ if (r>>19)&0x01 == 1 {
+ return fmt.Sprintf("%d(", int32(r|0xfff<<20))
+ } else {
+ return fmt.Sprintf("%d(", int32(r))
+ }
+}
+
+// Disp12 represents an 12-bit Unsigned Displacement
+type Disp12 uint16
+
+func (Disp12) IsArg() {}
+func (r Disp12) String(pc uint64) string {
+ return fmt.Sprintf("%d(", r)
+}
+
+// RegIm12 represents an 12-bit Register immediate number.
+type RegIm12 uint16
+
+func (RegIm12) IsArg() {}
+func (r RegIm12) String(pc uint64) string {
+ if (r>>11)&0x01 == 1 {
+ return fmt.Sprintf("%#x", pc+(2*uint64(int16(r|0xf<<12))))
+ } else {
+ return fmt.Sprintf("%#x", pc+(2*uint64(int16(r))))
+ }
+}
+
+// RegIm16 represents an 16-bit Register immediate number.
+type RegIm16 uint16
+
+func (RegIm16) IsArg() {}
+func (r RegIm16) String(pc uint64) string {
+ return fmt.Sprintf("%#x", pc+(2*uint64(int16(r))))
+}
+
+// RegIm24 represents an 24-bit Register immediate number.
+type RegIm24 uint32
+
+func (RegIm24) IsArg() {}
+func (r RegIm24) String(pc uint64) string {
+ if (r>>23)&0x01 == 1 {
+ return fmt.Sprintf("%#x", pc+(2*uint64(int32(r|0xff<<24))))
+ } else {
+ return fmt.Sprintf("%#x", pc+(2*uint64(int32(r))))
+ }
+}
+
+// RegIm32 represents an 32-bit Register immediate number.
+type RegIm32 uint32
+
+func (RegIm32) IsArg() {}
+func (r RegIm32) String(pc uint64) string {
+ return fmt.Sprintf("%#x", pc+(2*uint64(int32(r))))
+}
+
+// A Reg is a single register. The zero value means R0, not the absence of a register.
+// It also includes special registers.
+type Reg uint16
+
+const (
+ R0 Reg = iota
+ R1
+ R2
+ R3
+ R4
+ R5
+ R6
+ R7
+ R8
+ R9
+ R10
+ R11
+ R12
+ R13
+ R14
+ R15
+ F0
+ F1
+ F2
+ F3
+ F4
+ F5
+ F6
+ F7
+ F8
+ F9
+ F10
+ F11
+ F12
+ F13
+ F14
+ F15
+ A0
+ A1
+ A2
+ A3
+ A4
+ A5
+ A6
+ A7
+ A8
+ A9
+ A10
+ A11
+ A12
+ A13
+ A14
+ A15
+ C0
+ C1
+ C2
+ C3
+ C4
+ C5
+ C6
+ C7
+ C8
+ C9
+ C10
+ C11
+ C12
+ C13
+ C14
+ C15
+)
+
+func (Reg) IsArg() {}
+func (r Reg) String(pc uint64) string {
+ s := "%"
+ switch {
+ case R0 <= r && r <= R15:
+ return fmt.Sprintf("%sr%d", s, int(r-R0))
+ case F0 <= r && r <= F15:
+ return fmt.Sprintf("%sf%d", s, int(r-F0))
+ case A0 <= r && r <= A15:
+ return fmt.Sprintf("%sa%d", s, int(r-A0))
+ case C0 <= r && r <= C15:
+ return fmt.Sprintf("%sc%d", s, int(r-C0))
+ default:
+ return fmt.Sprintf("Reg(%d)", int(r))
+ }
+}
+
+// VReg is a vector register. The zero value means V0, not the absence of a register.
+
+type VReg uint8
+
+const (
+ V0 VReg = iota
+ V1
+ V2
+ V3
+ V4
+ V5
+ V6
+ V7
+ V8
+ V9
+ V10
+ V11
+ V12
+ V13
+ V14
+ V15
+ V16
+ V17
+ V18
+ V19
+ V20
+ V21
+ V22
+ V23
+ V24
+ V25
+ V26
+ V27
+ V28
+ V29
+ V30
+ V31
+)
+
+func (VReg) IsArg() {}
+func (r VReg) String(pc uint64) string {
+ s := "%"
+ if V0 <= r && r <= V31 {
+ return fmt.Sprintf("%sv%d", s, int(r-V0))
+ } else {
+ return fmt.Sprintf("VReg(%d)", int(r))
+ }
+}
+
+// Imm represents an immediate number.
+type Imm uint32
+
+func (Imm) IsArg() {}
+func (i Imm) String(pc uint64) string {
+ return fmt.Sprintf("%d", uint32(i))
+}
+
+// Sign8 represents an 8-bit signed immediate number.
+type Sign8 int8
+
+func (Sign8) IsArg() {}
+func (i Sign8) String(pc uint64) string {
+ return fmt.Sprintf("%d", i)
+}
+
+// Sign16 represents an 16-bit signed immediate number.
+type Sign16 int16
+
+func (Sign16) IsArg() {}
+func (i Sign16) String(pc uint64) string {
+ return fmt.Sprintf("%d", i)
+}
+
+// Sign32 represents an 32-bit signed immediate number.
+type Sign32 int32
+
+func (Sign32) IsArg() {}
+func (i Sign32) String(pc uint64) string {
+ return fmt.Sprintf("%d", i)
+}
+
+// Mask represents an 4-bit mask value
+type Mask uint8
+
+func (Mask) IsArg() {}
+func (i Mask) String(pc uint64) string {
+ return fmt.Sprintf("%d", i)
+}
+
+// Len represents an 8-bit type holds 4/8-bit Len argument
+type Len uint8
+
+func (Len) IsArg() {}
+func (i Len) String(pc uint64) string {
+ return fmt.Sprintf("%d,", uint16(i)+1)
+}
diff --git a/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/tables.go b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/tables.go
new file mode 100644
index 0000000000000000000000000000000000000000..f0db5e90850e646b817953594cb49539f7c9471c
--- /dev/null
+++ b/src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/tables.go
@@ -0,0 +1,5046 @@
+// Code generated by s390xmap -fmt=decoder ../s390x.csv DO NOT EDIT.
+
+package s390xasm
+
+const (
+ _ Op = iota
+ A
+ AR
+ ARK
+ AY
+ AG
+ AGR
+ AGRK
+ AGF
+ AGFR
+ AXBR
+ AXTR
+ AXTRA
+ ADB
+ ADBR
+ ADTR
+ ADTRA
+ AEB
+ AEBR
+ AP
+ AH
+ AHY
+ AGH
+ AHI
+ AGHI
+ AHHHR
+ AHHLR
+ AFI
+ AHIK
+ ASI
+ AGHIK
+ AGFI
+ AGSI
+ AIH
+ AL
+ ALR
+ ALRK
+ ALY
+ ALG
+ ALGR
+ ALGRK
+ ALGF
+ ALGFR
+ ALHHHR
+ ALHHLR
+ ALFI
+ ALGFI
+ ALC
+ ALCR
+ ALCG
+ ALCGR
+ ALHSIK
+ ALSI
+ ALGHSIK
+ ALGSI
+ ALSIH
+ ALSIHN
+ AXR
+ AD
+ ADR
+ AE
+ AER
+ AW
+ AWR
+ AU
+ AUR
+ N
+ NR
+ NRK
+ NY
+ NG
+ NGR
+ NGRK
+ NC
+ NI
+ NIY
+ NIHH
+ NIHL
+ NIHF
+ NILH
+ NILL
+ NILF
+ NCRK
+ NCGRK
+ BAL
+ BALR
+ BAS
+ BASR
+ BASSM
+ BSA
+ BSM
+ BAKR
+ BSG
+ BIC
+ BC
+ BCR
+ BCT
+ BCTR
+ BCTG
+ BCTGR
+ BXH
+ BXHG
+ BXLE
+ BXLEG
+ BPP
+ BPRP
+ BRAS
+ BRASL
+ BRC
+ BRCL
+ BRCT
+ BRCTG
+ BRCTH
+ BRXH
+ BRXHG
+ BRXLE
+ BRXLG
+ XSCH
+ CKSM
+ KM
+ KMA
+ KMC
+ KMF
+ KMCTR
+ KMO
+ CSCH
+ C
+ CR
+ CY
+ CG
+ CGR
+ CGF
+ CGFR
+ CXBR
+ CXTR
+ CXR
+ CDB
+ CDBR
+ CDTR
+ CD
+ CDR
+ CEB
+ CEBR
+ CE
+ CER
+ CRB
+ CGRB
+ CRJ
+ CGRJ
+ CFC
+ CRDTE
+ KXBR
+ KXTR
+ KDB
+ KDBR
+ KDTR
+ KEB
+ KEBR
+ CS
+ CSY
+ CSG
+ CSP
+ CSPG
+ CSST
+ CRT
+ CGRT
+ CEXTR
+ CEDTR
+ CP
+ CDS
+ CDSY
+ CDSG
+ CH
+ CHY
+ CGH
+ CHHSI
+ CHI
+ CHSI
+ CGHI
+ CGHSI
+ CHRL
+ CGHRL
+ CHF
+ CHHR
+ CHLR
+ CFI
+ CGFI
+ CIB
+ CGIB
+ CIJ
+ CGIJ
+ CIT
+ CGIT
+ CIH
+ CL
+ CLR
+ CLY
+ CLG
+ CLGR
+ CLGF
+ CLGFR
+ CLC
+ CLI
+ CLIY
+ CLRB
+ CLGRB
+ CLRJ
+ CLGRJ
+ CLRT
+ CLT
+ CLGRT
+ CLGT
+ CLMH
+ CLM
+ CLMY
+ CLHF
+ CLHHR
+ CLHLR
+ CLHHSI
+ CLFI
+ CLFHSI
+ CLGHSI
+ CLGFI
+ CLIB
+ CLGIB
+ CLIJ
+ CLGIJ
+ CLFIT
+ CLGIT
+ CLIH
+ CLCL
+ CLCLE
+ CLCLU
+ CLRL
+ CLHRL
+ CLGRL
+ CLGHRL
+ CLGFRL
+ CLST
+ CRL
+ CGRL
+ CGFRL
+ CUSE
+ CMPSC
+ KDSA
+ KIMD
+ KLMD
+ KMAC
+ THDR
+ THDER
+ CXFBR
+ CXFBRA
+ CXFTR
+ CXFR
+ CDFBR
+ CDFBRA
+ CDFTR
+ CDFR
+ CEFBR
+ CEFBRA
+ CEFR
+ CXGBR
+ CXGBRA
+ CXGTR
+ CXGTRA
+ CXGR
+ CDGBR
+ CDGBRA
+ CDGTR
+ CDGTRA
+ CDGR
+ CEGBR
+ CEGBRA
+ CEGR
+ CXLFBR
+ CXLFTR
+ CDLFBR
+ CDLFTR
+ CELFBR
+ CXLGBR
+ CXLGTR
+ CDLGBR
+ CDLGTR
+ CELGBR
+ CXPT
+ CDPT
+ CXSTR
+ CDSTR
+ CXUTR
+ CDUTR
+ CXZT
+ CDZT
+ TBEDR
+ TBDR
+ CVB
+ CVBY
+ CVBG
+ CVD
+ CVDY
+ CVDG
+ CFXBR
+ CFXBRA
+ CGXBR
+ CGXBRA
+ CFXTR
+ CGXTR
+ CGXTRA
+ CFXR
+ CGXR
+ CFDBR
+ CFDBRA
+ CGDBR
+ CGDBRA
+ CFDTR
+ CGDTR
+ CGDTRA
+ CFDR
+ CGDR
+ CFEBR
+ CFEBRA
+ CGEBR
+ CGEBRA
+ CFER
+ CGER
+ CLFXBR
+ CLGXBR
+ CLFXTR
+ CLGXTR
+ CLFDBR
+ CLGDBR
+ CLFDTR
+ CLGDTR
+ CLFEBR
+ CLGEBR
+ CPXT
+ CPDT
+ CSXTR
+ CSDTR
+ CUXTR
+ CUDTR
+ CZXT
+ CZDT
+ CU24
+ CU21
+ CU12
+ CU14
+ CU42
+ CU41
+ CPYA
+ CPSDR
+ VSCSHP
+ VSCHP
+ DFLTCC
+ D
+ DR
+ DXBR
+ DXTR
+ DXTRA
+ DXR
+ DDB
+ DDBR
+ DDTR
+ DDTRA
+ DD
+ DDR
+ DEB
+ DEBR
+ DE
+ DER
+ DP
+ DL
+ DLR
+ DLG
+ DLGR
+ DSG
+ DSGR
+ DSGF
+ DSGFR
+ DIDBR
+ DIEBR
+ ED
+ EDMK
+ X
+ XR
+ XRK
+ XY
+ XG
+ XGR
+ XGRK
+ XC
+ XI
+ XIY
+ XIHF
+ XILF
+ EX
+ EXRL
+ EAR
+ ESEA
+ EEXTR
+ EEDTR
+ ECAG
+ ECTG
+ EFPC
+ EPAR
+ EPAIR
+ EPSW
+ ESAR
+ ESAIR
+ ESXTR
+ ESDTR
+ EREG
+ EREGG
+ ESTA
+ ETND
+ FLOGR
+ HSCH
+ HDR
+ HER
+ IAC
+ IEXTR
+ IEDTR
+ IC
+ ICY
+ ICMH
+ ICM
+ ICMY
+ IIHH
+ IIHL
+ IIHF
+ IILH
+ IILL
+ IILF
+ IPM
+ IPK
+ IRBM
+ ISKE
+ IVSK
+ IDTE
+ IPTE
+ L
+ LR
+ LY
+ LG
+ LGR
+ LGF
+ LGFR
+ LXR
+ LD
+ LDR
+ LDY
+ LE
+ LER
+ LEY
+ LAM
+ LAMY
+ LA
+ LAY
+ LAE
+ LAEY
+ LARL
+ LASP
+ LAA
+ LAAG
+ LAAL
+ LAALG
+ LAN
+ LANG
+ LAX
+ LAXG
+ LAO
+ LAOG
+ LT
+ LTR
+ LTG
+ LTGR
+ LTGF
+ LTGFR
+ LTXBR
+ LTXTR
+ LTXR
+ LTDBR
+ LTDTR
+ LTDR
+ LTEBR
+ LTER
+ LAT
+ LGAT
+ LZRF
+ LZRG
+ LBEAR
+ LB
+ LBR
+ LGB
+ LGBR
+ LBH
+ LCR
+ LCGR
+ LCGFR
+ LCXBR
+ LCXR
+ LCDBR
+ LCDR
+ LCDFR
+ LCEBR
+ LCER
+ LCTL
+ LCTLG
+ LCBB
+ FIXBR
+ FIXBRA
+ FIXTR
+ FIXR
+ FIDBR
+ FIDBRA
+ FIDTR
+ FIDR
+ FIEBR
+ FIEBRA
+ FIER
+ LFPC
+ LFAS
+ LDGR
+ LGDR
+ LGG
+ LGSC
+ LH
+ LHR
+ LHY
+ LGH
+ LGHR
+ LHH
+ LOCHHI
+ LHI
+ LGHI
+ LOCHI
+ LOCGHI
+ LHRL
+ LGHRL
+ LFH
+ LFHAT
+ LOCFH
+ LOCFHR
+ LGFI
+ LXDB
+ LXDBR
+ LXDTR
+ LXD
+ LXDR
+ LXEB
+ LXEBR
+ LXE
+ LXER
+ LDEB
+ LDEBR
+ LDETR
+ LDE
+ LDER
+ LLGF
+ LLGFR
+ LLGFSG
+ LLGFAT
+ LLZRGF
+ LLC
+ LLCR
+ LLGC
+ LLGCR
+ LLCH
+ LLH
+ LLHR
+ LLGH
+ LLGHR
+ LLHH
+ LLHRL
+ LLGHRL
+ LLIHH
+ LLIHL
+ LLIHF
+ LLILH
+ LLILL
+ LLILF
+ LLGFRL
+ LLGT
+ LLGTR
+ LLGTAT
+ LM
+ LMY
+ LMG
+ LMD
+ LMH
+ LNR
+ LNGR
+ LNGFR
+ LNXBR
+ LNXR
+ LNDBR
+ LNDR
+ LNDFR
+ LNEBR
+ LNER
+ LOC
+ LOCR
+ LOCG
+ LOCGR
+ LPTEA
+ LPD
+ LPDG
+ LPQ
+ LPR
+ LPGR
+ LPGFR
+ LPXBR
+ LPXR
+ LPDBR
+ LPDR
+ LPDFR
+ LPEBR
+ LPER
+ LPSW
+ LPSWE
+ LPSWEY
+ LRA
+ LRAY
+ LRAG
+ LRL
+ LGRL
+ LGFRL
+ LRVH
+ LRV
+ LRVR
+ LRVG
+ LRVGR
+ LDXBR
+ LDXBRA
+ LDXTR
+ LDXR
+ LRDR
+ LEXBR
+ LEXBRA
+ LEXR
+ LEDBR
+ LEDBRA
+ LEDTR
+ LEDR
+ LRER
+ LURA
+ LURAG
+ LZXR
+ LZDR
+ LZER
+ MSTA
+ MSCH
+ MC
+ MVHHI
+ MVHI
+ MVGHI
+ MVC
+ MVI
+ MVIY
+ MVCIN
+ MVCL
+ MVCLE
+ MVCLU
+ MVN
+ MVPG
+ MVCRL
+ MVST
+ MVCP
+ MVCS
+ MVCDK
+ MVCK
+ MVO
+ MVCOS
+ MVCSK
+ MVZ
+ MG
+ MGRK
+ M
+ MFY
+ MR
+ MXBR
+ MXTR
+ MXTRA
+ MXR
+ MDB
+ MDBR
+ MDTR
+ MDTRA
+ MD
+ MDR
+ MXDB
+ MXDBR
+ MXD
+ MXDR
+ MEEB
+ MEEBR
+ MEE
+ MEER
+ MDEB
+ MDEBR
+ MDE
+ MDER
+ ME
+ MER
+ MAY
+ MAYR
+ MADB
+ MADBR
+ MAD
+ MADR
+ MAEB
+ MAEBR
+ MAE
+ MAER
+ MAYH
+ MAYHR
+ MAYL
+ MAYLR
+ MSDB
+ MSDBR
+ MSD
+ MSDR
+ MSEB
+ MSEBR
+ MSE
+ MSER
+ MP
+ MH
+ MHY
+ MGH
+ MHI
+ MGHI
+ MLG
+ MLGR
+ ML
+ MLR
+ MS
+ MSC
+ MSR
+ MSRKC
+ MSY
+ MSG
+ MSGC
+ MSGR
+ MSGRKC
+ MSGF
+ MSGFR
+ MSFI
+ MSGFI
+ MYH
+ MYHR
+ MYL
+ MYLR
+ MY
+ MYR
+ NNRK
+ NNGRK
+ NNPA
+ NIAI
+ NTSTG
+ NORK
+ NOGRK
+ NXRK
+ NXGRK
+ O
+ OR
+ ORK
+ OY
+ OG
+ OGR
+ OGRK
+ OC
+ OI
+ OIY
+ OIHH
+ OIHL
+ OIHF
+ OILH
+ OILL
+ OILF
+ OCRK
+ OCGRK
+ PACK
+ PKA
+ PKU
+ PGIN
+ PGOUT
+ PCC
+ PCKMO
+ PFPO
+ PFMF
+ PLO
+ PPA
+ PRNO
+ PTFF
+ PTF
+ POPCNT
+ PFD
+ PFDRL
+ PC
+ PR
+ PT
+ PTI
+ PALB
+ PTLB
+ QAXTR
+ QADTR
+ QPACI
+ RRXTR
+ RRDTR
+ RCHP
+ RDP
+ RRBE
+ RRBM
+ RP
+ RSCH
+ RLL
+ RLLG
+ RNSBG
+ RXSBG
+ RISBG
+ RISBGN
+ RISBHG
+ RISBLG
+ ROSBG
+ SRST
+ SRSTU
+ SELR
+ SELGR
+ SELFHR
+ SAR
+ SAL
+ SAC
+ SACF
+ SAM24
+ SAM31
+ SAM64
+ SRNM
+ SRNMB
+ SCHM
+ SCK
+ SCKC
+ SCKPF
+ SPT
+ SRNMT
+ SFPC
+ SFASR
+ SPX
+ SPM
+ SPKA
+ SSAR
+ SSAIR
+ SSKE
+ SSM
+ SRP
+ SLDA
+ SLDL
+ SLA
+ SLAK
+ SLAG
+ SLL
+ SLLK
+ SLLG
+ SRDA
+ SRDL
+ SRA
+ SRAK
+ SRAG
+ SRL
+ SRLK
+ SRLG
+ SLXT
+ SLDT
+ SRXT
+ SRDT
+ SIGP
+ SORTL
+ SQXBR
+ SQXR
+ SQDB
+ SQDBR
+ SQD
+ SQDR
+ SQEB
+ SQEBR
+ SQE
+ SQER
+ SSCH
+ ST
+ STY
+ STG
+ STD
+ STDY
+ STE
+ STEY
+ STAM
+ STAMY
+ STBEAR
+ STCPS
+ STCRW
+ STC
+ STCY
+ STCH
+ STCMH
+ STCM
+ STCMY
+ STCK
+ STCKC
+ STCKE
+ STCKF
+ STCTL
+ STCTG
+ STAP
+ STIDP
+ STPT
+ STFL
+ STFLE
+ STFPC
+ STGSC
+ STH
+ STHY
+ STHH
+ STHRL
+ STFH
+ STOCFH
+ STM
+ STMY
+ STMG
+ STMH
+ STOC
+ STOCG
+ STPQ
+ STPX
+ STRAG
+ STRL
+ STGRL
+ STRVH
+ STRV
+ STRVG
+ STSCH
+ STSI
+ STNSM
+ STOSM
+ STURA
+ STURG
+ S
+ SR
+ SRK
+ SY
+ SG
+ SGR
+ SGRK
+ SGF
+ SGFR
+ SXBR
+ SXTR
+ SXTRA
+ SDB
+ SDBR
+ SDTR
+ SDTRA
+ SEB
+ SEBR
+ SP
+ SH
+ SHY
+ SGH
+ SHHHR
+ SHHLR
+ SL
+ SLR
+ SLRK
+ SLY
+ SLG
+ SLGR
+ SLGRK
+ SLGF
+ SLGFR
+ SLHHHR
+ SLHHLR
+ SLFI
+ SLGFI
+ SLB
+ SLBR
+ SLBG
+ SLBGR
+ SXR
+ SD
+ SDR
+ SE
+ SER
+ SW
+ SWR
+ SU
+ SUR
+ SVC
+ TAR
+ TAM
+ TS
+ TB
+ TCXB
+ TDCXT
+ TCDB
+ TDCDT
+ TCEB
+ TDCET
+ TDGXT
+ TDGDT
+ TDGET
+ TP
+ TPEI
+ TPI
+ TPROT
+ TSCH
+ TM
+ TMY
+ TMHH
+ TMHL
+ TMLH
+ TMLL
+ TMH
+ TML
+ TRACE
+ TRACG
+ TABORT
+ TBEGINC
+ TBEGIN
+ TEND
+ TR
+ TRT
+ TRTE
+ TRTR
+ TRTRE
+ TRE
+ TROO
+ TROT
+ TRTO
+ TRTT
+ TRAP2
+ TRAP4
+ UNPK
+ UNPKA
+ UNPKU
+ UPT
+ VA
+ VACC
+ VAP
+ VAC
+ VACCC
+ VN
+ VNC
+ VAVG
+ VAVGL
+ VBPERM
+ VCKSM
+ VCP
+ VCEQ
+ VCH
+ VCHL
+ VCSPH
+ VCVB
+ VCVBG
+ VCVD
+ VCVDG
+ VCLZDP
+ VCLZ
+ VCTZ
+ VDP
+ VEC
+ VECL
+ VERIM
+ VERLL
+ VERLLV
+ VESLV
+ VESL
+ VESRA
+ VESRAV
+ VESRL
+ VESRLV
+ VX
+ VFAE
+ VFEE
+ VFENE
+ VFA
+ WFK
+ VFCE
+ VFCH
+ VFCHE
+ WFC
+ VCLFNH
+ VCLFNL
+ VCRNF
+ VCFPS
+ VCDG
+ VCFPL
+ VCDLG
+ VCFN
+ VCSFP
+ VCGD
+ VCLFP
+ VCLGD
+ VCNF
+ VFD
+ VFLL
+ VFLR
+ VFMAX
+ VFMIN
+ VFM
+ VFMA
+ VFMS
+ VFNMA
+ VFNMS
+ VFPSO
+ VFSQ
+ VFS
+ VFTCI
+ VGFM
+ VGFMA
+ VGEF
+ VGEG
+ VGBM
+ VGM
+ VISTR
+ VL
+ VLR
+ VLREP
+ VLEBRH
+ VLEBRF
+ VLEBRG
+ VLBRREP
+ VLLEBRZ
+ VLBR
+ VLC
+ VLEH
+ VLEF
+ VLEG
+ VLEB
+ VLEIH
+ VLEIF
+ VLEIG
+ VLEIB
+ VLER
+ VFI
+ VLGV
+ VLIP
+ VLLEZ
+ VLM
+ VLP
+ VLRL
+ VLRLR
+ VLBB
+ VLVG
+ VLVGP
+ VLL
+ VMX
+ VMXL
+ VMRH
+ VMRL
+ VMN
+ VMNL
+ VMAE
+ VMAH
+ VMALE
+ VMALH
+ VMALO
+ VMAL
+ VMAO
+ VMSP
+ VMP
+ VME
+ VMH
+ VMLE
+ VMLH
+ VMLO
+ VML
+ VMO
+ VMSL
+ VNN
+ VNO
+ VNX
+ VO
+ VOC
+ VPK
+ VPKLS
+ VPKS
+ VPKZ
+ VPKZR
+ VPSOP
+ VPERM
+ VPDI
+ VPOPCT
+ VRP
+ VREP
+ VREPI
+ VSCEF
+ VSCEG
+ VSEL
+ VSDP
+ VSRP
+ VSRPR
+ VSL
+ VSLB
+ VSLD
+ VSLDB
+ VSRA
+ VSRAB
+ VSRD
+ VSRL
+ VSRLB
+ VSEG
+ VST
+ VSTEBRH
+ VSTEBRF
+ VSTEBRG
+ VSTBR
+ VSTEH
+ VSTEF
+ VSTEG
+ VSTEB
+ VSTER
+ VSTM
+ VSTRL
+ VSTRLR
+ VSTL
+ VSTRC
+ VSTRS
+ VS
+ VSCBI
+ VSP
+ VSBCBI
+ VSBI
+ VSUMG
+ VSUMQ
+ VSUM
+ VTP
+ VTM
+ VUPH
+ VUPLH
+ VUPLL
+ VUPL
+ VUPKZ
+ VUPKZH
+ VUPKZL
+ ZAP
+)
+
+var opstr = [...]string{
+ A: "a",
+ AR: "ar",
+ ARK: "ark",
+ AY: "ay",
+ AG: "ag",
+ AGR: "agr",
+ AGRK: "agrk",
+ AGF: "agf",
+ AGFR: "agfr",
+ AXBR: "axbr",
+ AXTR: "axtr",
+ AXTRA: "axtra",
+ ADB: "adb",
+ ADBR: "adbr",
+ ADTR: "adtr",
+ ADTRA: "adtra",
+ AEB: "aeb",
+ AEBR: "aebr",
+ AP: "ap",
+ AH: "ah",
+ AHY: "ahy",
+ AGH: "agh",
+ AHI: "ahi",
+ AGHI: "aghi",
+ AHHHR: "ahhhr",
+ AHHLR: "ahhlr",
+ AFI: "afi",
+ AHIK: "ahik",
+ ASI: "asi",
+ AGHIK: "aghik",
+ AGFI: "agfi",
+ AGSI: "agsi",
+ AIH: "aih",
+ AL: "al",
+ ALR: "alr",
+ ALRK: "alrk",
+ ALY: "aly",
+ ALG: "alg",
+ ALGR: "algr",
+ ALGRK: "algrk",
+ ALGF: "algf",
+ ALGFR: "algfr",
+ ALHHHR: "alhhhr",
+ ALHHLR: "alhhlr",
+ ALFI: "alfi",
+ ALGFI: "algfi",
+ ALC: "alc",
+ ALCR: "alcr",
+ ALCG: "alcg",
+ ALCGR: "alcgr",
+ ALHSIK: "alhsik",
+ ALSI: "alsi",
+ ALGHSIK: "alghsik",
+ ALGSI: "algsi",
+ ALSIH: "alsih",
+ ALSIHN: "alsihn",
+ AXR: "axr",
+ AD: "ad",
+ ADR: "adr",
+ AE: "ae",
+ AER: "aer",
+ AW: "aw",
+ AWR: "awr",
+ AU: "au",
+ AUR: "aur",
+ N: "n",
+ NR: "nr",
+ NRK: "nrk",
+ NY: "ny",
+ NG: "ng",
+ NGR: "ngr",
+ NGRK: "ngrk",
+ NC: "nc",
+ NI: "ni",
+ NIY: "niy",
+ NIHH: "nihh",
+ NIHL: "nihl",
+ NIHF: "nihf",
+ NILH: "nilh",
+ NILL: "nill",
+ NILF: "nilf",
+ NCRK: "ncrk",
+ NCGRK: "ncgrk",
+ BAL: "bal",
+ BALR: "balr",
+ BAS: "bas",
+ BASR: "basr",
+ BASSM: "bassm",
+ BSA: "bsa",
+ BSM: "bsm",
+ BAKR: "bakr",
+ BSG: "bsg",
+ BIC: "bic",
+ BC: "bc",
+ BCR: "bcr",
+ BCT: "bct",
+ BCTR: "bctr",
+ BCTG: "bctg",
+ BCTGR: "bctgr",
+ BXH: "bxh",
+ BXHG: "bxhg",
+ BXLE: "bxle",
+ BXLEG: "bxleg",
+ BPP: "bpp",
+ BPRP: "bprp",
+ BRAS: "bras",
+ BRASL: "brasl",
+ BRC: "brc",
+ BRCL: "brcl",
+ BRCT: "brct",
+ BRCTG: "brctg",
+ BRCTH: "brcth",
+ BRXH: "brxh",
+ BRXHG: "brxhg",
+ BRXLE: "brxle",
+ BRXLG: "brxlg",
+ XSCH: "xsch",
+ CKSM: "cksm",
+ KM: "km",
+ KMA: "kma",
+ KMC: "kmc",
+ KMF: "kmf",
+ KMCTR: "kmctr",
+ KMO: "kmo",
+ CSCH: "csch",
+ C: "c",
+ CR: "cr",
+ CY: "cy",
+ CG: "cg",
+ CGR: "cgr",
+ CGF: "cgf",
+ CGFR: "cgfr",
+ CXBR: "cxbr",
+ CXTR: "cxtr",
+ CXR: "cxr",
+ CDB: "cdb",
+ CDBR: "cdbr",
+ CDTR: "cdtr",
+ CD: "cd",
+ CDR: "cdr",
+ CEB: "ceb",
+ CEBR: "cebr",
+ CE: "ce",
+ CER: "cer",
+ CRB: "crb",
+ CGRB: "cgrb",
+ CRJ: "crj",
+ CGRJ: "cgrj",
+ CFC: "cfc",
+ CRDTE: "crdte",
+ KXBR: "kxbr",
+ KXTR: "kxtr",
+ KDB: "kdb",
+ KDBR: "kdbr",
+ KDTR: "kdtr",
+ KEB: "keb",
+ KEBR: "kebr",
+ CS: "cs",
+ CSY: "csy",
+ CSG: "csg",
+ CSP: "csp",
+ CSPG: "cspg",
+ CSST: "csst",
+ CRT: "crt",
+ CGRT: "cgrt",
+ CEXTR: "cextr",
+ CEDTR: "cedtr",
+ CP: "cp",
+ CDS: "cds",
+ CDSY: "cdsy",
+ CDSG: "cdsg",
+ CH: "ch",
+ CHY: "chy",
+ CGH: "cgh",
+ CHHSI: "chhsi",
+ CHI: "chi",
+ CHSI: "chsi",
+ CGHI: "cghi",
+ CGHSI: "cghsi",
+ CHRL: "chrl",
+ CGHRL: "cghrl",
+ CHF: "chf",
+ CHHR: "chhr",
+ CHLR: "chlr",
+ CFI: "cfi",
+ CGFI: "cgfi",
+ CIB: "cib",
+ CGIB: "cgib",
+ CIJ: "cij",
+ CGIJ: "cgij",
+ CIT: "cit",
+ CGIT: "cgit",
+ CIH: "cih",
+ CL: "cl",
+ CLR: "clr",
+ CLY: "cly",
+ CLG: "clg",
+ CLGR: "clgr",
+ CLGF: "clgf",
+ CLGFR: "clgfr",
+ CLC: "clc",
+ CLI: "cli",
+ CLIY: "cliy",
+ CLRB: "clrb",
+ CLGRB: "clgrb",
+ CLRJ: "clrj",
+ CLGRJ: "clgrj",
+ CLRT: "clrt",
+ CLT: "clt",
+ CLGRT: "clgrt",
+ CLGT: "clgt",
+ CLMH: "clmh",
+ CLM: "clm",
+ CLMY: "clmy",
+ CLHF: "clhf",
+ CLHHR: "clhhr",
+ CLHLR: "clhlr",
+ CLHHSI: "clhhsi",
+ CLFI: "clfi",
+ CLFHSI: "clfhsi",
+ CLGHSI: "clghsi",
+ CLGFI: "clgfi",
+ CLIB: "clib",
+ CLGIB: "clgib",
+ CLIJ: "clij",
+ CLGIJ: "clgij",
+ CLFIT: "clfit",
+ CLGIT: "clgit",
+ CLIH: "clih",
+ CLCL: "clcl",
+ CLCLE: "clcle",
+ CLCLU: "clclu",
+ CLRL: "clrl",
+ CLHRL: "clhrl",
+ CLGRL: "clgrl",
+ CLGHRL: "clghrl",
+ CLGFRL: "clgfrl",
+ CLST: "clst",
+ CRL: "crl",
+ CGRL: "cgrl",
+ CGFRL: "cgfrl",
+ CUSE: "cuse",
+ CMPSC: "cmpsc",
+ KDSA: "kdsa",
+ KIMD: "kimd",
+ KLMD: "klmd",
+ KMAC: "kmac",
+ THDR: "thdr",
+ THDER: "thder",
+ CXFBR: "cxfbr",
+ CXFBRA: "cxfbra",
+ CXFTR: "cxftr",
+ CXFR: "cxfr",
+ CDFBR: "cdfbr",
+ CDFBRA: "cdfbra",
+ CDFTR: "cdftr",
+ CDFR: "cdfr",
+ CEFBR: "cefbr",
+ CEFBRA: "cefbra",
+ CEFR: "cefr",
+ CXGBR: "cxgbr",
+ CXGBRA: "cxgbra",
+ CXGTR: "cxgtr",
+ CXGTRA: "cxgtra",
+ CXGR: "cxgr",
+ CDGBR: "cdgbr",
+ CDGBRA: "cdgbra",
+ CDGTR: "cdgtr",
+ CDGTRA: "cdgtra",
+ CDGR: "cdgr",
+ CEGBR: "cegbr",
+ CEGBRA: "cegbra",
+ CEGR: "cegr",
+ CXLFBR: "cxlfbr",
+ CXLFTR: "cxlftr",
+ CDLFBR: "cdlfbr",
+ CDLFTR: "cdlftr",
+ CELFBR: "celfbr",
+ CXLGBR: "cxlgbr",
+ CXLGTR: "cxlgtr",
+ CDLGBR: "cdlgbr",
+ CDLGTR: "cdlgtr",
+ CELGBR: "celgbr",
+ CXPT: "cxpt",
+ CDPT: "cdpt",
+ CXSTR: "cxstr",
+ CDSTR: "cdstr",
+ CXUTR: "cxutr",
+ CDUTR: "cdutr",
+ CXZT: "cxzt",
+ CDZT: "cdzt",
+ TBEDR: "tbedr",
+ TBDR: "tbdr",
+ CVB: "cvb",
+ CVBY: "cvby",
+ CVBG: "cvbg",
+ CVD: "cvd",
+ CVDY: "cvdy",
+ CVDG: "cvdg",
+ CFXBR: "cfxbr",
+ CFXBRA: "cfxbra",
+ CGXBR: "cgxbr",
+ CGXBRA: "cgxbra",
+ CFXTR: "cfxtr",
+ CGXTR: "cgxtr",
+ CGXTRA: "cgxtra",
+ CFXR: "cfxr",
+ CGXR: "cgxr",
+ CFDBR: "cfdbr",
+ CFDBRA: "cfdbra",
+ CGDBR: "cgdbr",
+ CGDBRA: "cgdbra",
+ CFDTR: "cfdtr",
+ CGDTR: "cgdtr",
+ CGDTRA: "cgdtra",
+ CFDR: "cfdr",
+ CGDR: "cgdr",
+ CFEBR: "cfebr",
+ CFEBRA: "cfebra",
+ CGEBR: "cgebr",
+ CGEBRA: "cgebra",
+ CFER: "cfer",
+ CGER: "cger",
+ CLFXBR: "clfxbr",
+ CLGXBR: "clgxbr",
+ CLFXTR: "clfxtr",
+ CLGXTR: "clgxtr",
+ CLFDBR: "clfdbr",
+ CLGDBR: "clgdbr",
+ CLFDTR: "clfdtr",
+ CLGDTR: "clgdtr",
+ CLFEBR: "clfebr",
+ CLGEBR: "clgebr",
+ CPXT: "cpxt",
+ CPDT: "cpdt",
+ CSXTR: "csxtr",
+ CSDTR: "csdtr",
+ CUXTR: "cuxtr",
+ CUDTR: "cudtr",
+ CZXT: "czxt",
+ CZDT: "czdt",
+ CU24: "cu24",
+ CU21: "cu21",
+ CU12: "cu12",
+ CU14: "cu14",
+ CU42: "cu42",
+ CU41: "cu41",
+ CPYA: "cpya",
+ CPSDR: "cpsdr",
+ VSCSHP: "vscshp",
+ VSCHP: "vschp",
+ DFLTCC: "dfltcc",
+ D: "d",
+ DR: "dr",
+ DXBR: "dxbr",
+ DXTR: "dxtr",
+ DXTRA: "dxtra",
+ DXR: "dxr",
+ DDB: "ddb",
+ DDBR: "ddbr",
+ DDTR: "ddtr",
+ DDTRA: "ddtra",
+ DD: "dd",
+ DDR: "ddr",
+ DEB: "deb",
+ DEBR: "debr",
+ DE: "de",
+ DER: "der",
+ DP: "dp",
+ DL: "dl",
+ DLR: "dlr",
+ DLG: "dlg",
+ DLGR: "dlgr",
+ DSG: "dsg",
+ DSGR: "dsgr",
+ DSGF: "dsgf",
+ DSGFR: "dsgfr",
+ DIDBR: "didbr",
+ DIEBR: "diebr",
+ ED: "ed",
+ EDMK: "edmk",
+ X: "x",
+ XR: "xr",
+ XRK: "xrk",
+ XY: "xy",
+ XG: "xg",
+ XGR: "xgr",
+ XGRK: "xgrk",
+ XC: "xc",
+ XI: "xi",
+ XIY: "xiy",
+ XIHF: "xihf",
+ XILF: "xilf",
+ EX: "ex",
+ EXRL: "exrl",
+ EAR: "ear",
+ ESEA: "esea",
+ EEXTR: "eextr",
+ EEDTR: "eedtr",
+ ECAG: "ecag",
+ ECTG: "ectg",
+ EFPC: "efpc",
+ EPAR: "epar",
+ EPAIR: "epair",
+ EPSW: "epsw",
+ ESAR: "esar",
+ ESAIR: "esair",
+ ESXTR: "esxtr",
+ ESDTR: "esdtr",
+ EREG: "ereg",
+ EREGG: "eregg",
+ ESTA: "esta",
+ ETND: "etnd",
+ FLOGR: "flogr",
+ HSCH: "hsch",
+ HDR: "hdr",
+ HER: "her",
+ IAC: "iac",
+ IEXTR: "iextr",
+ IEDTR: "iedtr",
+ IC: "ic",
+ ICY: "icy",
+ ICMH: "icmh",
+ ICM: "icm",
+ ICMY: "icmy",
+ IIHH: "iihh",
+ IIHL: "iihl",
+ IIHF: "iihf",
+ IILH: "iilh",
+ IILL: "iill",
+ IILF: "iilf",
+ IPM: "ipm",
+ IPK: "ipk",
+ IRBM: "irbm",
+ ISKE: "iske",
+ IVSK: "ivsk",
+ IDTE: "idte",
+ IPTE: "ipte",
+ L: "l",
+ LR: "lr",
+ LY: "ly",
+ LG: "lg",
+ LGR: "lgr",
+ LGF: "lgf",
+ LGFR: "lgfr",
+ LXR: "lxr",
+ LD: "ld",
+ LDR: "ldr",
+ LDY: "ldy",
+ LE: "le",
+ LER: "ler",
+ LEY: "ley",
+ LAM: "lam",
+ LAMY: "lamy",
+ LA: "la",
+ LAY: "lay",
+ LAE: "lae",
+ LAEY: "laey",
+ LARL: "larl",
+ LASP: "lasp",
+ LAA: "laa",
+ LAAG: "laag",
+ LAAL: "laal",
+ LAALG: "laalg",
+ LAN: "lan",
+ LANG: "lang",
+ LAX: "lax",
+ LAXG: "laxg",
+ LAO: "lao",
+ LAOG: "laog",
+ LT: "lt",
+ LTR: "ltr",
+ LTG: "ltg",
+ LTGR: "ltgr",
+ LTGF: "ltgf",
+ LTGFR: "ltgfr",
+ LTXBR: "ltxbr",
+ LTXTR: "ltxtr",
+ LTXR: "ltxr",
+ LTDBR: "ltdbr",
+ LTDTR: "ltdtr",
+ LTDR: "ltdr",
+ LTEBR: "ltebr",
+ LTER: "lter",
+ LAT: "lat",
+ LGAT: "lgat",
+ LZRF: "lzrf",
+ LZRG: "lzrg",
+ LBEAR: "lbear",
+ LB: "lb",
+ LBR: "lbr",
+ LGB: "lgb",
+ LGBR: "lgbr",
+ LBH: "lbh",
+ LCR: "lcr",
+ LCGR: "lcgr",
+ LCGFR: "lcgfr",
+ LCXBR: "lcxbr",
+ LCXR: "lcxr",
+ LCDBR: "lcdbr",
+ LCDR: "lcdr",
+ LCDFR: "lcdfr",
+ LCEBR: "lcebr",
+ LCER: "lcer",
+ LCTL: "lctl",
+ LCTLG: "lctlg",
+ LCBB: "lcbb",
+ FIXBR: "fixbr",
+ FIXBRA: "fixbra",
+ FIXTR: "fixtr",
+ FIXR: "fixr",
+ FIDBR: "fidbr",
+ FIDBRA: "fidbra",
+ FIDTR: "fidtr",
+ FIDR: "fidr",
+ FIEBR: "fiebr",
+ FIEBRA: "fiebra",
+ FIER: "fier",
+ LFPC: "lfpc",
+ LFAS: "lfas",
+ LDGR: "ldgr",
+ LGDR: "lgdr",
+ LGG: "lgg",
+ LGSC: "lgsc",
+ LH: "lh",
+ LHR: "lhr",
+ LHY: "lhy",
+ LGH: "lgh",
+ LGHR: "lghr",
+ LHH: "lhh",
+ LOCHHI: "lochhi",
+ LHI: "lhi",
+ LGHI: "lghi",
+ LOCHI: "lochi",
+ LOCGHI: "locghi",
+ LHRL: "lhrl",
+ LGHRL: "lghrl",
+ LFH: "lfh",
+ LFHAT: "lfhat",
+ LOCFH: "locfh",
+ LOCFHR: "locfhr",
+ LGFI: "lgfi",
+ LXDB: "lxdb",
+ LXDBR: "lxdbr",
+ LXDTR: "lxdtr",
+ LXD: "lxd",
+ LXDR: "lxdr",
+ LXEB: "lxeb",
+ LXEBR: "lxebr",
+ LXE: "lxe",
+ LXER: "lxer",
+ LDEB: "ldeb",
+ LDEBR: "ldebr",
+ LDETR: "ldetr",
+ LDE: "lde",
+ LDER: "lder",
+ LLGF: "llgf",
+ LLGFR: "llgfr",
+ LLGFSG: "llgfsg",
+ LLGFAT: "llgfat",
+ LLZRGF: "llzrgf",
+ LLC: "llc",
+ LLCR: "llcr",
+ LLGC: "llgc",
+ LLGCR: "llgcr",
+ LLCH: "llch",
+ LLH: "llh",
+ LLHR: "llhr",
+ LLGH: "llgh",
+ LLGHR: "llghr",
+ LLHH: "llhh",
+ LLHRL: "llhrl",
+ LLGHRL: "llghrl",
+ LLIHH: "llihh",
+ LLIHL: "llihl",
+ LLIHF: "llihf",
+ LLILH: "llilh",
+ LLILL: "llill",
+ LLILF: "llilf",
+ LLGFRL: "llgfrl",
+ LLGT: "llgt",
+ LLGTR: "llgtr",
+ LLGTAT: "llgtat",
+ LM: "lm",
+ LMY: "lmy",
+ LMG: "lmg",
+ LMD: "lmd",
+ LMH: "lmh",
+ LNR: "lnr",
+ LNGR: "lngr",
+ LNGFR: "lngfr",
+ LNXBR: "lnxbr",
+ LNXR: "lnxr",
+ LNDBR: "lndbr",
+ LNDR: "lndr",
+ LNDFR: "lndfr",
+ LNEBR: "lnebr",
+ LNER: "lner",
+ LOC: "loc",
+ LOCR: "locr",
+ LOCG: "locg",
+ LOCGR: "locgr",
+ LPTEA: "lptea",
+ LPD: "lpd",
+ LPDG: "lpdg",
+ LPQ: "lpq",
+ LPR: "lpr",
+ LPGR: "lpgr",
+ LPGFR: "lpgfr",
+ LPXBR: "lpxbr",
+ LPXR: "lpxr",
+ LPDBR: "lpdbr",
+ LPDR: "lpdr",
+ LPDFR: "lpdfr",
+ LPEBR: "lpebr",
+ LPER: "lper",
+ LPSW: "lpsw",
+ LPSWE: "lpswe",
+ LPSWEY: "lpswey",
+ LRA: "lra",
+ LRAY: "lray",
+ LRAG: "lrag",
+ LRL: "lrl",
+ LGRL: "lgrl",
+ LGFRL: "lgfrl",
+ LRVH: "lrvh",
+ LRV: "lrv",
+ LRVR: "lrvr",
+ LRVG: "lrvg",
+ LRVGR: "lrvgr",
+ LDXBR: "ldxbr",
+ LDXBRA: "ldxbra",
+ LDXTR: "ldxtr",
+ LDXR: "ldxr",
+ LRDR: "lrdr",
+ LEXBR: "lexbr",
+ LEXBRA: "lexbra",
+ LEXR: "lexr",
+ LEDBR: "ledbr",
+ LEDBRA: "ledbra",
+ LEDTR: "ledtr",
+ LEDR: "ledr",
+ LRER: "lrer",
+ LURA: "lura",
+ LURAG: "lurag",
+ LZXR: "lzxr",
+ LZDR: "lzdr",
+ LZER: "lzer",
+ MSTA: "msta",
+ MSCH: "msch",
+ MC: "mc",
+ MVHHI: "mvhhi",
+ MVHI: "mvhi",
+ MVGHI: "mvghi",
+ MVC: "mvc",
+ MVI: "mvi",
+ MVIY: "mviy",
+ MVCIN: "mvcin",
+ MVCL: "mvcl",
+ MVCLE: "mvcle",
+ MVCLU: "mvclu",
+ MVN: "mvn",
+ MVPG: "mvpg",
+ MVCRL: "mvcrl",
+ MVST: "mvst",
+ MVCP: "mvcp",
+ MVCS: "mvcs",
+ MVCDK: "mvcdk",
+ MVCK: "mvck",
+ MVO: "mvo",
+ MVCOS: "mvcos",
+ MVCSK: "mvcsk",
+ MVZ: "mvz",
+ MG: "mg",
+ MGRK: "mgrk",
+ M: "m",
+ MFY: "mfy",
+ MR: "mr",
+ MXBR: "mxbr",
+ MXTR: "mxtr",
+ MXTRA: "mxtra",
+ MXR: "mxr",
+ MDB: "mdb",
+ MDBR: "mdbr",
+ MDTR: "mdtr",
+ MDTRA: "mdtra",
+ MD: "md",
+ MDR: "mdr",
+ MXDB: "mxdb",
+ MXDBR: "mxdbr",
+ MXD: "mxd",
+ MXDR: "mxdr",
+ MEEB: "meeb",
+ MEEBR: "meebr",
+ MEE: "mee",
+ MEER: "meer",
+ MDEB: "mdeb",
+ MDEBR: "mdebr",
+ MDE: "mde",
+ MDER: "mder",
+ ME: "me",
+ MER: "mer",
+ MAY: "may",
+ MAYR: "mayr",
+ MADB: "madb",
+ MADBR: "madbr",
+ MAD: "mad",
+ MADR: "madr",
+ MAEB: "maeb",
+ MAEBR: "maebr",
+ MAE: "mae",
+ MAER: "maer",
+ MAYH: "mayh",
+ MAYHR: "mayhr",
+ MAYL: "mayl",
+ MAYLR: "maylr",
+ MSDB: "msdb",
+ MSDBR: "msdbr",
+ MSD: "msd",
+ MSDR: "msdr",
+ MSEB: "mseb",
+ MSEBR: "msebr",
+ MSE: "mse",
+ MSER: "mser",
+ MP: "mp",
+ MH: "mh",
+ MHY: "mhy",
+ MGH: "mgh",
+ MHI: "mhi",
+ MGHI: "mghi",
+ MLG: "mlg",
+ MLGR: "mlgr",
+ ML: "ml",
+ MLR: "mlr",
+ MS: "ms",
+ MSC: "msc",
+ MSR: "msr",
+ MSRKC: "msrkc",
+ MSY: "msy",
+ MSG: "msg",
+ MSGC: "msgc",
+ MSGR: "msgr",
+ MSGRKC: "msgrkc",
+ MSGF: "msgf",
+ MSGFR: "msgfr",
+ MSFI: "msfi",
+ MSGFI: "msgfi",
+ MYH: "myh",
+ MYHR: "myhr",
+ MYL: "myl",
+ MYLR: "mylr",
+ MY: "my",
+ MYR: "myr",
+ NNRK: "nnrk",
+ NNGRK: "nngrk",
+ NNPA: "nnpa",
+ NIAI: "niai",
+ NTSTG: "ntstg",
+ NORK: "nork",
+ NOGRK: "nogrk",
+ NXRK: "nxrk",
+ NXGRK: "nxgrk",
+ O: "o",
+ OR: "or",
+ ORK: "ork",
+ OY: "oy",
+ OG: "og",
+ OGR: "ogr",
+ OGRK: "ogrk",
+ OC: "oc",
+ OI: "oi",
+ OIY: "oiy",
+ OIHH: "oihh",
+ OIHL: "oihl",
+ OIHF: "oihf",
+ OILH: "oilh",
+ OILL: "oill",
+ OILF: "oilf",
+ OCRK: "ocrk",
+ OCGRK: "ocgrk",
+ PACK: "pack",
+ PKA: "pka",
+ PKU: "pku",
+ PGIN: "pgin",
+ PGOUT: "pgout",
+ PCC: "pcc",
+ PCKMO: "pckmo",
+ PFPO: "pfpo",
+ PFMF: "pfmf",
+ PLO: "plo",
+ PPA: "ppa",
+ PRNO: "prno",
+ PTFF: "ptff",
+ PTF: "ptf",
+ POPCNT: "popcnt",
+ PFD: "pfd",
+ PFDRL: "pfdrl",
+ PC: "pc",
+ PR: "pr",
+ PT: "pt",
+ PTI: "pti",
+ PALB: "palb",
+ PTLB: "ptlb",
+ QAXTR: "qaxtr",
+ QADTR: "qadtr",
+ QPACI: "qpaci",
+ RRXTR: "rrxtr",
+ RRDTR: "rrdtr",
+ RCHP: "rchp",
+ RDP: "rdp",
+ RRBE: "rrbe",
+ RRBM: "rrbm",
+ RP: "rp",
+ RSCH: "rsch",
+ RLL: "rll",
+ RLLG: "rllg",
+ RNSBG: "rnsbg",
+ RXSBG: "rxsbg",
+ RISBG: "risbg",
+ RISBGN: "risbgn",
+ RISBHG: "risbhg",
+ RISBLG: "risblg",
+ ROSBG: "rosbg",
+ SRST: "srst",
+ SRSTU: "srstu",
+ SELR: "selr",
+ SELGR: "selgr",
+ SELFHR: "selfhr",
+ SAR: "sar",
+ SAL: "sal",
+ SAC: "sac",
+ SACF: "sacf",
+ SAM24: "sam24",
+ SAM31: "sam31",
+ SAM64: "sam64",
+ SRNM: "srnm",
+ SRNMB: "srnmb",
+ SCHM: "schm",
+ SCK: "sck",
+ SCKC: "sckc",
+ SCKPF: "sckpf",
+ SPT: "spt",
+ SRNMT: "srnmt",
+ SFPC: "sfpc",
+ SFASR: "sfasr",
+ SPX: "spx",
+ SPM: "spm",
+ SPKA: "spka",
+ SSAR: "ssar",
+ SSAIR: "ssair",
+ SSKE: "sske",
+ SSM: "ssm",
+ SRP: "srp",
+ SLDA: "slda",
+ SLDL: "sldl",
+ SLA: "sla",
+ SLAK: "slak",
+ SLAG: "slag",
+ SLL: "sll",
+ SLLK: "sllk",
+ SLLG: "sllg",
+ SRDA: "srda",
+ SRDL: "srdl",
+ SRA: "sra",
+ SRAK: "srak",
+ SRAG: "srag",
+ SRL: "srl",
+ SRLK: "srlk",
+ SRLG: "srlg",
+ SLXT: "slxt",
+ SLDT: "sldt",
+ SRXT: "srxt",
+ SRDT: "srdt",
+ SIGP: "sigp",
+ SORTL: "sortl",
+ SQXBR: "sqxbr",
+ SQXR: "sqxr",
+ SQDB: "sqdb",
+ SQDBR: "sqdbr",
+ SQD: "sqd",
+ SQDR: "sqdr",
+ SQEB: "sqeb",
+ SQEBR: "sqebr",
+ SQE: "sqe",
+ SQER: "sqer",
+ SSCH: "ssch",
+ ST: "st",
+ STY: "sty",
+ STG: "stg",
+ STD: "std",
+ STDY: "stdy",
+ STE: "ste",
+ STEY: "stey",
+ STAM: "stam",
+ STAMY: "stamy",
+ STBEAR: "stbear",
+ STCPS: "stcps",
+ STCRW: "stcrw",
+ STC: "stc",
+ STCY: "stcy",
+ STCH: "stch",
+ STCMH: "stcmh",
+ STCM: "stcm",
+ STCMY: "stcmy",
+ STCK: "stck",
+ STCKC: "stckc",
+ STCKE: "stcke",
+ STCKF: "stckf",
+ STCTL: "stctl",
+ STCTG: "stctg",
+ STAP: "stap",
+ STIDP: "stidp",
+ STPT: "stpt",
+ STFL: "stfl",
+ STFLE: "stfle",
+ STFPC: "stfpc",
+ STGSC: "stgsc",
+ STH: "sth",
+ STHY: "sthy",
+ STHH: "sthh",
+ STHRL: "sthrl",
+ STFH: "stfh",
+ STOCFH: "stocfh",
+ STM: "stm",
+ STMY: "stmy",
+ STMG: "stmg",
+ STMH: "stmh",
+ STOC: "stoc",
+ STOCG: "stocg",
+ STPQ: "stpq",
+ STPX: "stpx",
+ STRAG: "strag",
+ STRL: "strl",
+ STGRL: "stgrl",
+ STRVH: "strvh",
+ STRV: "strv",
+ STRVG: "strvg",
+ STSCH: "stsch",
+ STSI: "stsi",
+ STNSM: "stnsm",
+ STOSM: "stosm",
+ STURA: "stura",
+ STURG: "sturg",
+ S: "s",
+ SR: "sr",
+ SRK: "srk",
+ SY: "sy",
+ SG: "sg",
+ SGR: "sgr",
+ SGRK: "sgrk",
+ SGF: "sgf",
+ SGFR: "sgfr",
+ SXBR: "sxbr",
+ SXTR: "sxtr",
+ SXTRA: "sxtra",
+ SDB: "sdb",
+ SDBR: "sdbr",
+ SDTR: "sdtr",
+ SDTRA: "sdtra",
+ SEB: "seb",
+ SEBR: "sebr",
+ SP: "sp",
+ SH: "sh",
+ SHY: "shy",
+ SGH: "sgh",
+ SHHHR: "shhhr",
+ SHHLR: "shhlr",
+ SL: "sl",
+ SLR: "slr",
+ SLRK: "slrk",
+ SLY: "sly",
+ SLG: "slg",
+ SLGR: "slgr",
+ SLGRK: "slgrk",
+ SLGF: "slgf",
+ SLGFR: "slgfr",
+ SLHHHR: "slhhhr",
+ SLHHLR: "slhhlr",
+ SLFI: "slfi",
+ SLGFI: "slgfi",
+ SLB: "slb",
+ SLBR: "slbr",
+ SLBG: "slbg",
+ SLBGR: "slbgr",
+ SXR: "sxr",
+ SD: "sd",
+ SDR: "sdr",
+ SE: "se",
+ SER: "ser",
+ SW: "sw",
+ SWR: "swr",
+ SU: "su",
+ SUR: "sur",
+ SVC: "svc",
+ TAR: "tar",
+ TAM: "tam",
+ TS: "ts",
+ TB: "tb",
+ TCXB: "tcxb",
+ TDCXT: "tdcxt",
+ TCDB: "tcdb",
+ TDCDT: "tdcdt",
+ TCEB: "tceb",
+ TDCET: "tdcet",
+ TDGXT: "tdgxt",
+ TDGDT: "tdgdt",
+ TDGET: "tdget",
+ TP: "tp",
+ TPEI: "tpei",
+ TPI: "tpi",
+ TPROT: "tprot",
+ TSCH: "tsch",
+ TM: "tm",
+ TMY: "tmy",
+ TMHH: "tmhh",
+ TMHL: "tmhl",
+ TMLH: "tmlh",
+ TMLL: "tmll",
+ TMH: "tmh",
+ TML: "tml",
+ TRACE: "trace",
+ TRACG: "tracg",
+ TABORT: "tabort",
+ TBEGINC: "tbeginc",
+ TBEGIN: "tbegin",
+ TEND: "tend",
+ TR: "tr",
+ TRT: "trt",
+ TRTE: "trte",
+ TRTR: "trtr",
+ TRTRE: "trtre",
+ TRE: "tre",
+ TROO: "troo",
+ TROT: "trot",
+ TRTO: "trto",
+ TRTT: "trtt",
+ TRAP2: "trap2",
+ TRAP4: "trap4",
+ UNPK: "unpk",
+ UNPKA: "unpka",
+ UNPKU: "unpku",
+ UPT: "upt",
+ VA: "va",
+ VACC: "vacc",
+ VAP: "vap",
+ VAC: "vac",
+ VACCC: "vaccc",
+ VN: "vn",
+ VNC: "vnc",
+ VAVG: "vavg",
+ VAVGL: "vavgl",
+ VBPERM: "vbperm",
+ VCKSM: "vcksm",
+ VCP: "vcp",
+ VCEQ: "vceq",
+ VCH: "vch",
+ VCHL: "vchl",
+ VCSPH: "vcsph",
+ VCVB: "vcvb",
+ VCVBG: "vcvbg",
+ VCVD: "vcvd",
+ VCVDG: "vcvdg",
+ VCLZDP: "vclzdp",
+ VCLZ: "vclz",
+ VCTZ: "vctz",
+ VDP: "vdp",
+ VEC: "vec",
+ VECL: "vecl",
+ VERIM: "verim",
+ VERLL: "verll",
+ VERLLV: "verllv",
+ VESLV: "veslv",
+ VESL: "vesl",
+ VESRA: "vesra",
+ VESRAV: "vesrav",
+ VESRL: "vesrl",
+ VESRLV: "vesrlv",
+ VX: "vx",
+ VFAE: "vfae",
+ VFEE: "vfee",
+ VFENE: "vfene",
+ VFA: "vfa",
+ WFK: "wfk",
+ VFCE: "vfce",
+ VFCH: "vfch",
+ VFCHE: "vfche",
+ WFC: "wfc",
+ VCLFNH: "vclfnh",
+ VCLFNL: "vclfnl",
+ VCRNF: "vcrnf",
+ VCFPS: "vcfps",
+ VCDG: "vcdg",
+ VCFPL: "vcfpl",
+ VCDLG: "vcdlg",
+ VCFN: "vcfn",
+ VCSFP: "vcsfp",
+ VCGD: "vcgd",
+ VCLFP: "vclfp",
+ VCLGD: "vclgd",
+ VCNF: "vcnf",
+ VFD: "vfd",
+ VFLL: "vfll",
+ VFLR: "vflr",
+ VFMAX: "vfmax",
+ VFMIN: "vfmin",
+ VFM: "vfm",
+ VFMA: "vfma",
+ VFMS: "vfms",
+ VFNMA: "vfnma",
+ VFNMS: "vfnms",
+ VFPSO: "vfpso",
+ VFSQ: "vfsq",
+ VFS: "vfs",
+ VFTCI: "vftci",
+ VGFM: "vgfm",
+ VGFMA: "vgfma",
+ VGEF: "vgef",
+ VGEG: "vgeg",
+ VGBM: "vgbm",
+ VGM: "vgm",
+ VISTR: "vistr",
+ VL: "vl",
+ VLR: "vlr",
+ VLREP: "vlrep",
+ VLEBRH: "vlebrh",
+ VLEBRF: "vlebrf",
+ VLEBRG: "vlebrg",
+ VLBRREP: "vlbrrep",
+ VLLEBRZ: "vllebrz",
+ VLBR: "vlbr",
+ VLC: "vlc",
+ VLEH: "vleh",
+ VLEF: "vlef",
+ VLEG: "vleg",
+ VLEB: "vleb",
+ VLEIH: "vleih",
+ VLEIF: "vleif",
+ VLEIG: "vleig",
+ VLEIB: "vleib",
+ VLER: "vler",
+ VFI: "vfi",
+ VLGV: "vlgv",
+ VLIP: "vlip",
+ VLLEZ: "vllez",
+ VLM: "vlm",
+ VLP: "vlp",
+ VLRL: "vlrl",
+ VLRLR: "vlrlr",
+ VLBB: "vlbb",
+ VLVG: "vlvg",
+ VLVGP: "vlvgp",
+ VLL: "vll",
+ VMX: "vmx",
+ VMXL: "vmxl",
+ VMRH: "vmrh",
+ VMRL: "vmrl",
+ VMN: "vmn",
+ VMNL: "vmnl",
+ VMAE: "vmae",
+ VMAH: "vmah",
+ VMALE: "vmale",
+ VMALH: "vmalh",
+ VMALO: "vmalo",
+ VMAL: "vmal",
+ VMAO: "vmao",
+ VMSP: "vmsp",
+ VMP: "vmp",
+ VME: "vme",
+ VMH: "vmh",
+ VMLE: "vmle",
+ VMLH: "vmlh",
+ VMLO: "vmlo",
+ VML: "vml",
+ VMO: "vmo",
+ VMSL: "vmsl",
+ VNN: "vnn",
+ VNO: "vno",
+ VNX: "vnx",
+ VO: "vo",
+ VOC: "voc",
+ VPK: "vpk",
+ VPKLS: "vpkls",
+ VPKS: "vpks",
+ VPKZ: "vpkz",
+ VPKZR: "vpkzr",
+ VPSOP: "vpsop",
+ VPERM: "vperm",
+ VPDI: "vpdi",
+ VPOPCT: "vpopct",
+ VRP: "vrp",
+ VREP: "vrep",
+ VREPI: "vrepi",
+ VSCEF: "vscef",
+ VSCEG: "vsceg",
+ VSEL: "vsel",
+ VSDP: "vsdp",
+ VSRP: "vsrp",
+ VSRPR: "vsrpr",
+ VSL: "vsl",
+ VSLB: "vslb",
+ VSLD: "vsld",
+ VSLDB: "vsldb",
+ VSRA: "vsra",
+ VSRAB: "vsrab",
+ VSRD: "vsrd",
+ VSRL: "vsrl",
+ VSRLB: "vsrlb",
+ VSEG: "vseg",
+ VST: "vst",
+ VSTEBRH: "vstebrh",
+ VSTEBRF: "vstebrf",
+ VSTEBRG: "vstebrg",
+ VSTBR: "vstbr",
+ VSTEH: "vsteh",
+ VSTEF: "vstef",
+ VSTEG: "vsteg",
+ VSTEB: "vsteb",
+ VSTER: "vster",
+ VSTM: "vstm",
+ VSTRL: "vstrl",
+ VSTRLR: "vstrlr",
+ VSTL: "vstl",
+ VSTRC: "vstrc",
+ VSTRS: "vstrs",
+ VS: "vs",
+ VSCBI: "vscbi",
+ VSP: "vsp",
+ VSBCBI: "vsbcbi",
+ VSBI: "vsbi",
+ VSUMG: "vsumg",
+ VSUMQ: "vsumq",
+ VSUM: "vsum",
+ VTP: "vtp",
+ VTM: "vtm",
+ VUPH: "vuph",
+ VUPLH: "vuplh",
+ VUPLL: "vupll",
+ VUPL: "vupl",
+ VUPKZ: "vupkz",
+ VUPKZH: "vupkzh",
+ VUPKZL: "vupkzl",
+ ZAP: "zap",
+}
+
+var (
+ ap_Reg_8_11 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{8, 4}}
+ ap_DispUnsigned_20_31 = &argField{Type: TypeDispUnsigned, flags: 0x10, BitField: BitField{20, 12}}
+ ap_IndexReg_12_15 = &argField{Type: TypeIndexReg, flags: 0x41, BitField: BitField{12, 4}}
+ ap_BaseReg_16_19 = &argField{Type: TypeBaseReg, flags: 0x21, BitField: BitField{16, 4}}
+ ap_Reg_12_15 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{12, 4}}
+ ap_Reg_24_27 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{24, 4}}
+ ap_Reg_28_31 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{28, 4}}
+ ap_Reg_16_19 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{16, 4}}
+ ap_DispSigned20_20_39 = &argField{Type: TypeDispSigned20, flags: 0x10, BitField: BitField{20, 20}}
+ ap_FPReg_24_27 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{24, 4}}
+ ap_FPReg_28_31 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{28, 4}}
+ ap_FPReg_16_19 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{16, 4}}
+ ap_Mask_20_23 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{20, 4}}
+ ap_FPReg_8_11 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{8, 4}}
+ ap_Len_8_11 = &argField{Type: TypeLen, flags: 0x10, BitField: BitField{8, 4}}
+ ap_DispUnsigned_36_47 = &argField{Type: TypeDispUnsigned, flags: 0x10, BitField: BitField{36, 12}}
+ ap_Len_12_15 = &argField{Type: TypeLen, flags: 0x10, BitField: BitField{12, 4}}
+ ap_BaseReg_32_35 = &argField{Type: TypeBaseReg, flags: 0x21, BitField: BitField{32, 4}}
+ ap_ImmSigned16_16_31 = &argField{Type: TypeImmSigned16, flags: 0x0, BitField: BitField{16, 16}}
+ ap_ImmSigned32_16_47 = &argField{Type: TypeImmSigned32, flags: 0x0, BitField: BitField{16, 32}}
+ ap_ImmSigned8_8_15 = &argField{Type: TypeImmSigned8, flags: 0x0, BitField: BitField{8, 8}}
+ ap_ImmUnsigned_16_47 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 32}}
+ ap_FPReg_12_15 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{12, 4}}
+ ap_Len_8_15 = &argField{Type: TypeLen, flags: 0x10, BitField: BitField{8, 8}}
+ ap_ImmUnsigned_8_15 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{8, 8}}
+ ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 16}}
+ ap_Mask_8_11 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{8, 4}}
+ ap_RegImSigned16_32_47 = &argField{Type: TypeRegImSigned16, flags: 0x80, BitField: BitField{32, 16}}
+ ap_RegImSigned12_12_23 = &argField{Type: TypeRegImSigned12, flags: 0x80, BitField: BitField{12, 12}}
+ ap_RegImSigned24_24_47 = &argField{Type: TypeRegImSigned24, flags: 0x80, BitField: BitField{24, 24}}
+ ap_RegImSigned16_16_31 = &argField{Type: TypeRegImSigned16, flags: 0x80, BitField: BitField{16, 16}}
+ ap_RegImSigned32_16_47 = &argField{Type: TypeRegImSigned32, flags: 0x80, BitField: BitField{16, 32}}
+ ap_Mask_32_35 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{32, 4}}
+ ap_Mask_16_19 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{16, 4}}
+ ap_ImmSigned16_32_47 = &argField{Type: TypeImmSigned16, flags: 0x0, BitField: BitField{32, 16}}
+ ap_ImmSigned8_32_39 = &argField{Type: TypeImmSigned8, flags: 0x0, BitField: BitField{32, 8}}
+ ap_Mask_12_15 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{12, 4}}
+ ap_ImmUnsigned_32_47 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 16}}
+ ap_ImmUnsigned_32_39 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 8}}
+ ap_FPReg_32_35 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{32, 4}}
+ ap_Mask_36_39 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{36, 4}}
+ ap_ACReg_24_27 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{24, 4}}
+ ap_ACReg_28_31 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{28, 4}}
+ ap_VecReg_8_11 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{8, 4}}
+ ap_VecReg_12_15 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{12, 4}}
+ ap_VecReg_16_19 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{16, 4}}
+ ap_ImmUnsigned_36_39 = &argField{Type: TypeImmUnsigned, flags: 0xc00, BitField: BitField{36, 4}}
+ ap_Mask_24_27 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{24, 4}}
+ ap_ACReg_8_11 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{8, 4}}
+ ap_ACReg_12_15 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{12, 4}}
+ ap_CReg_8_11 = &argField{Type: TypeCReg, flags: 0x4, BitField: BitField{8, 4}}
+ ap_CReg_12_15 = &argField{Type: TypeCReg, flags: 0x4, BitField: BitField{12, 4}}
+ ap_ImmUnsigned_24_27 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{24, 4}}
+ ap_ImmUnsigned_28_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{28, 4}}
+ ap_ImmUnsigned_16_23 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 8}}
+ ap_ImmUnsigned_24_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{24, 8}}
+ ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{12, 4}}
+ ap_ImmUnsigned_28_35 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{28, 8}}
+ ap_VecReg_32_35 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{32, 4}}
+ ap_Mask_28_31 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{28, 4}}
+ ap_ImmUnsigned_16_27 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 12}}
+ ap_ImmUnsigned_32_35 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 4}}
+)
+
+var instFormats = [...]instFormat{
+ {A, 0xff00000000000000, 0x5a00000000000000, 0x0, // ADD (32) (A R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AR, 0xff00000000000000, 0x1a00000000000000, 0x0, // ADD (32) (AR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {ARK, 0xffff000000000000, 0xb9f8000000000000, 0xf0000000000, // ADD (32) (ARK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {AY, 0xff00000000ff0000, 0xe3000000005a0000, 0x0, // ADD (32) (AY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AG, 0xff00000000ff0000, 0xe300000000080000, 0x0, // ADD (64) (AG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AGR, 0xffff000000000000, 0xb908000000000000, 0xff0000000000, // ADD (64) (AGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {AGRK, 0xffff000000000000, 0xb9e8000000000000, 0xf0000000000, // ADD (64) (AGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {AGF, 0xff00000000ff0000, 0xe300000000180000, 0x0, // ADD (64←32) (AGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AGFR, 0xffff000000000000, 0xb918000000000000, 0xff0000000000, // ADD (64←32) (AGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {AXBR, 0xffff000000000000, 0xb34a000000000000, 0xff0000000000, // ADD (extended BFP) (AXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {AXTR, 0xffff000000000000, 0xb3da000000000000, 0xf0000000000, // ADD (extended DFP) (AXTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {AXTRA, 0xffff000000000000, 0xb3da000000000000, 0x0, // ADD (extended DFP) (AXTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {ADB, 0xff00000000ff0000, 0xed000000001a0000, 0xff000000, // ADD (long BFP) (ADB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ADBR, 0xffff000000000000, 0xb31a000000000000, 0xff0000000000, // ADD (long BFP) (ADBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {ADTR, 0xffff000000000000, 0xb3d2000000000000, 0xf0000000000, // ADD (long DFP) (ADTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {ADTRA, 0xffff000000000000, 0xb3d2000000000000, 0x0, // ADD (long DFP) (ADTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {AEB, 0xff00000000ff0000, 0xed000000000a0000, 0xff000000, // ADD (short BFP) (AEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AEBR, 0xffff000000000000, 0xb30a000000000000, 0xff0000000000, // ADD (short BFP) (AEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {AP, 0xff00000000000000, 0xfa00000000000000, 0x0, // ADD DECIMAL (AP D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {AH, 0xff00000000000000, 0x4a00000000000000, 0x0, // ADD HALFWORD (32←16) (AH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AHY, 0xff00000000ff0000, 0xe3000000007a0000, 0x0, // ADD HALFWORD (32←16) (AHY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AGH, 0xff00000000ff0000, 0xe300000000380000, 0x0, // ADD HALFWORD (64→16) (AGH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AHI, 0xff0f000000000000, 0xa70a000000000000, 0x0, // ADD HALFWORD IMMEDIATE (32←16) (AHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
+ {AGHI, 0xff0f000000000000, 0xa70b000000000000, 0x0, // ADD HALFWORD IMMEDIATE (64←16) (AGHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
+ {AHHHR, 0xffff000000000000, 0xb9c8000000000000, 0xf0000000000, // ADD HIGH (32) (AHHHR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {AHHLR, 0xffff000000000000, 0xb9d8000000000000, 0xf0000000000, // ADD HIGH (32) (AHHLR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {AFI, 0xff0f000000000000, 0xc209000000000000, 0x0, // ADD IMMEDIATE (32) (AFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
+ {AHIK, 0xff00000000ff0000, 0xec00000000d80000, 0xff000000, // ADD IMMEDIATE (32←16) (AHIK R1,R3,I2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}},
+ {ASI, 0xff00000000ff0000, 0xeb000000006a0000, 0x0, // ADD IMMEDIATE (32←8) (ASI D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
+ {AGHIK, 0xff00000000ff0000, 0xec00000000d90000, 0xff000000, // ADD IMMEDIATE (64←16) (AGHIK R1,R3,I2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}},
+ {AGFI, 0xff0f000000000000, 0xc208000000000000, 0x0, // ADD IMMEDIATE (64←32) (AGFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
+ {AGSI, 0xff00000000ff0000, 0xeb000000007a0000, 0x0, // ADD IMMEDIATE (64←8) (AGSI D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
+ {AIH, 0xff0f000000000000, 0xcc08000000000000, 0x0, // ADD IMMEDIATE HIGH (32) (AIH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
+ {AL, 0xff00000000000000, 0x5e00000000000000, 0x0, // ADD LOGICAL (32) (AL R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ALR, 0xff00000000000000, 0x1e00000000000000, 0x0, // ADD LOGICAL (32) (ALR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {ALRK, 0xffff000000000000, 0xb9fa000000000000, 0xf0000000000, // ADD LOGICAL (32) (ALRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {ALY, 0xff00000000ff0000, 0xe3000000005e0000, 0x0, // ADD LOGICAL (32) (ALY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ALG, 0xff00000000ff0000, 0xe3000000000a0000, 0x0, // ADD LOGICAL (64) (ALG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ALGR, 0xffff000000000000, 0xb90a000000000000, 0xff0000000000, // ADD LOGICAL (64) (ALGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ALGRK, 0xffff000000000000, 0xb9ea000000000000, 0xf0000000000, // ADD LOGICAL (64) (ALGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {ALGF, 0xff00000000ff0000, 0xe3000000001a0000, 0x0, // ADD LOGICAL (64←32) (ALGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ALGFR, 0xffff000000000000, 0xb91a000000000000, 0xff0000000000, // ADD LOGICAL (64←32) (ALGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ALHHHR, 0xffff000000000000, 0xb9ca000000000000, 0xf0000000000, // ADD LOGICAL HIGH (32) (ALHHHR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {ALHHLR, 0xffff000000000000, 0xb9da000000000000, 0xf0000000000, // ADD LOGICAL HIGH (32) (ALHHLR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {ALFI, 0xff0f000000000000, 0xc20b000000000000, 0x0, // ADD LOGICAL IMMEDIATE (32) (ALFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {ALGFI, 0xff0f000000000000, 0xc20a000000000000, 0x0, // ADD LOGICAL IMMEDIATE (64←32) (ALGFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {ALC, 0xff00000000ff0000, 0xe300000000980000, 0x0, // ADD LOGICAL WITH CARRY (32) (ALC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ALCR, 0xffff000000000000, 0xb998000000000000, 0xff0000000000, // ADD LOGICAL WITH CARRY (32) (ALCR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ALCG, 0xff00000000ff0000, 0xe300000000880000, 0x0, // ADD LOGICAL WITH CARRY (64) (ALCG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ALCGR, 0xffff000000000000, 0xb988000000000000, 0xff0000000000, // ADD LOGICAL WITH CARRY (64) (ALCGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ALHSIK, 0xff00000000ff0000, 0xec00000000da0000, 0xff000000, // ADD LOGICAL WITH SIGNED IMMEDIATE(32→16) (ALHSIK R1,R3,I2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}},
+ {ALSI, 0xff00000000ff0000, 0xeb000000006e0000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE (32←8) (ALSI D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
+ {ALGHSIK, 0xff00000000ff0000, 0xec00000000db0000, 0xff000000, // ADD LOGICAL WITH SIGNED IMMEDIATE(64→16) (ALGHSIK R1,R3,I2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}},
+ {ALGSI, 0xff00000000ff0000, 0xeb000000007e0000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE (64→8) (ALGSI D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
+ {ALSIH, 0xff0f000000000000, 0xcc0a000000000000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE HIGH(32) (ALSIH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {ALSIHN, 0xff0f000000000000, 0xcc0b000000000000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE HIGH(32) (ALSIHN R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {AXR, 0xff00000000000000, 0x3600000000000000, 0x0, // ADD NORMALIZED (extended HFP) (AXR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {AD, 0xff00000000000000, 0x6a00000000000000, 0x0, // ADD NORMALIZED (long HFP) (AD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ADR, 0xff00000000000000, 0x2a00000000000000, 0x0, // ADD NORMALIZED (long HFP) (ADR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {AE, 0xff00000000000000, 0x7a00000000000000, 0x0, // ADD NORMALIZED (short HFP) (AE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AER, 0xff00000000000000, 0x3a00000000000000, 0x0, // ADD NORMALIZED (short HFP) (AER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {AW, 0xff00000000000000, 0x6e00000000000000, 0x0, // ADD UNNORMALIZED (long HFP) (AW R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AWR, 0xff00000000000000, 0x2e00000000000000, 0x0, // ADD UNNORMALIZED (long HFP) (AWR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {AU, 0xff00000000000000, 0x7e00000000000000, 0x0, // ADD UNNORMALIZED (short HFP) (AU R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {AUR, 0xff00000000000000, 0x3e00000000000000, 0x0, // ADD UNNORMALIZED (short HFP) (AUR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {N, 0xff00000000000000, 0x5400000000000000, 0x0, // AND (32) (N R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {NR, 0xff00000000000000, 0x1400000000000000, 0x0, // AND (32) (NR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {NRK, 0xffff000000000000, 0xb9f4000000000000, 0xf0000000000, // AND (32) (NRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NY, 0xff00000000ff0000, 0xe300000000540000, 0x0, // AND (32) (NY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {NG, 0xff00000000ff0000, 0xe300000000800000, 0x0, // AND (64) (NG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {NGR, 0xffff000000000000, 0xb980000000000000, 0xff0000000000, // AND (64) (NGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {NGRK, 0xffff000000000000, 0xb9e4000000000000, 0xf0000000000, // AND (64) (NGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NC, 0xff00000000000000, 0xd400000000000000, 0x0, // AND (character) (NC D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {NI, 0xff00000000000000, 0x9400000000000000, 0x0, // AND (immediate) (NI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {NIY, 0xff00000000ff0000, 0xeb00000000540000, 0x0, // AND (immediate) (NIY D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {NIHH, 0xff0f000000000000, 0xa504000000000000, 0x0, // AND IMMEDIATE (high high) (NIHH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {NIHL, 0xff0f000000000000, 0xa505000000000000, 0x0, // AND IMMEDIATE (high low) (NIHL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {NIHF, 0xff0f000000000000, 0xc00a000000000000, 0x0, // AND IMMEDIATE (high) (NIHF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {NILH, 0xff0f000000000000, 0xa506000000000000, 0x0, // AND IMMEDIATE (low high) (NILH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {NILL, 0xff0f000000000000, 0xa507000000000000, 0x0, // AND IMMEDIATE (low low) (NILL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {NILF, 0xff0f000000000000, 0xc00b000000000000, 0x0, // AND IMMEDIATE (low) (NILF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {NCRK, 0xffff000000000000, 0xb9f5000000000000, 0xf0000000000, // AND WITH COMPLEMENT(32) (NCRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NCGRK, 0xffff000000000000, 0xb9e5000000000000, 0xf0000000000, // AND WITH COMPLEMENT(64) (NCGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {BAL, 0xff00000000000000, 0x4500000000000000, 0x0, // BRANCH AND LINK (BAL R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {BALR, 0xff00000000000000, 0x500000000000000, 0x0, // BRANCH AND LINK (BALR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {BAS, 0xff00000000000000, 0x4d00000000000000, 0x0, // BRANCH AND SAVE (BAS R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {BASR, 0xff00000000000000, 0xd00000000000000, 0x0, // BRANCH AND SAVE (BASR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {BASSM, 0xff00000000000000, 0xc00000000000000, 0x0, // BRANCH AND SAVE AND SET MODE (BASSM R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {BSA, 0xffff000000000000, 0xb25a000000000000, 0xff0000000000, // BRANCH AND SET AUTHORITY (BSA R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {BSM, 0xff00000000000000, 0xb00000000000000, 0x0, // BRANCH AND SET MODE (BSM R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {BAKR, 0xffff000000000000, 0xb240000000000000, 0xff0000000000, // BRANCH AND STACK (BAKR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {BSG, 0xffff000000000000, 0xb258000000000000, 0xff0000000000, // BRANCH IN SUBSPACE GROUP (BSG R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {BIC, 0xff00000000ff0000, 0xe300000000470000, 0x0, // BRANCH INDIRECT ON CONDITION (BIC M1,D2(X2,B2))
+ [8]*argField{ap_Mask_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {BC, 0xff00000000000000, 0x4700000000000000, 0x0, // BRANCH ON CONDITION (BC M1,D2(X2,B2))
+ [8]*argField{ap_Mask_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {BCR, 0xff00000000000000, 0x700000000000000, 0x0, // BRANCH ON CONDITION (BCR M1,R2)
+ [8]*argField{ap_Mask_8_11, ap_Reg_12_15}},
+ {BCT, 0xff00000000000000, 0x4600000000000000, 0x0, // BRANCH ON COUNT (32) (BCT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {BCTR, 0xff00000000000000, 0x600000000000000, 0x0, // BRANCH ON COUNT (32) (BCTR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {BCTG, 0xff00000000ff0000, 0xe300000000460000, 0x0, // BRANCH ON COUNT (64) (BCTG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {BCTGR, 0xffff000000000000, 0xb946000000000000, 0xff0000000000, // BRANCH ON COUNT (64) (BCTGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {BXH, 0xff00000000000000, 0x8600000000000000, 0x0, // BRANCH ON INDEX HIGH (32) (BXH R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {BXHG, 0xff00000000ff0000, 0xeb00000000440000, 0x0, // BRANCH ON INDEX HIGH (64) (BXHG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {BXLE, 0xff00000000000000, 0x8700000000000000, 0x0, // BRANCH ON INDEX LOW OR EQUAL (32) (BXLE R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {BXLEG, 0xff00000000ff0000, 0xeb00000000450000, 0x0, // BRANCH ON INDEX LOW OR EQUAL (64) (BXLEG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {BPP, 0xff00000000000000, 0xc700000000000000, 0xf000000000000, // BRANCH PREDICTION PRELOAD (BPP M1,RI2,D3(B3))
+ [8]*argField{ap_Mask_8_11, ap_RegImSigned16_32_47, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {BPRP, 0xff00000000000000, 0xc500000000000000, 0x0, // BRANCH PREDICTION RELATIVE PRELOAD (BPRP M1,RI2,RI3)
+ [8]*argField{ap_Mask_8_11, ap_RegImSigned12_12_23, ap_RegImSigned24_24_47}},
+ {BRAS, 0xff0f000000000000, 0xa705000000000000, 0x0, // BRANCH RELATIVE AND SAVE (BRAS R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned16_16_31}},
+ {BRASL, 0xff0f000000000000, 0xc005000000000000, 0x0, // BRANCH RELATIVE AND SAVE LONG (BRASL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {BRC, 0xff0f000000000000, 0xa704000000000000, 0x0, // BRANCH RELATIVE ON CONDITION (BRC M1,RI2)
+ [8]*argField{ap_Mask_8_11, ap_RegImSigned16_16_31}},
+ {BRCL, 0xff0f000000000000, 0xc004000000000000, 0x0, // BRANCH RELATIVE ON CONDITION LONG (BRCL M1,RI2)
+ [8]*argField{ap_Mask_8_11, ap_RegImSigned32_16_47}},
+ {BRCT, 0xff0f000000000000, 0xa706000000000000, 0x0, // BRANCH RELATIVE ON COUNT (32) (BRCT R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned16_16_31}},
+ {BRCTG, 0xff0f000000000000, 0xa707000000000000, 0x0, // BRANCH RELATIVE ON COUNT (64) (BRCTG R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned16_16_31}},
+ {BRCTH, 0xff0f000000000000, 0xcc06000000000000, 0x0, // BRANCH RELATIVE ON COUNT HIGH (32) (BRCTH R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {BRXH, 0xff00000000000000, 0x8400000000000000, 0x0, // BRANCH RELATIVE ON INDEX HIGH (32) (BRXH R1,R3,RI2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}},
+ {BRXHG, 0xff00000000ff0000, 0xec00000000440000, 0xff000000, // BRANCH RELATIVE ON INDEX HIGH (64) (BRXHG R1,R3,RI2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}},
+ {BRXLE, 0xff00000000000000, 0x8500000000000000, 0x0, // BRANCH RELATIVE ON INDEX LOW OR EQ. (32) (BRXLE R1,R3,RI2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}},
+ {BRXLG, 0xff00000000ff0000, 0xec00000000450000, 0xff000000, // BRANCH RELATIVE ON INDEX LOW OR EQ. (64) (BRXLG R1,R3,RI2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}},
+ {XSCH, 0xffff000000000000, 0xb276000000000000, 0xffff00000000, // CANCEL SUBCHANNEL (XSCH)
+ [8]*argField{}},
+ {CKSM, 0xffff000000000000, 0xb241000000000000, 0xff0000000000, // CHECKSUM (CKSM R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KM, 0xffff000000000000, 0xb92e000000000000, 0xff0000000000, // CIPHER MESSAGE (KM R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KMA, 0xffff000000000000, 0xb929000000000000, 0xf0000000000, // CIPHER MESSAGE WITH AUTHENTICATION (KMA R1,R3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31}},
+ {KMC, 0xffff000000000000, 0xb92f000000000000, 0xff0000000000, // CIPHER MESSAGE WITH CHAINING (KMC R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KMF, 0xffff000000000000, 0xb92a000000000000, 0xff0000000000, // CIPHER MESSAGE WITH CIPHER FEEDBACK (KMF R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KMCTR, 0xffff000000000000, 0xb92d000000000000, 0xf0000000000, // CIPHER MESSAGE WITH COUNTER (KMCTR R1,R3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31}},
+ {KMO, 0xffff000000000000, 0xb92b000000000000, 0xff0000000000, // CIPHER MESSAGE WITH OUTPUT FEEDBACK (KMO R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CSCH, 0xffff000000000000, 0xb230000000000000, 0xffff00000000, // CLEAR SUBCHANNEL (CSCH)
+ [8]*argField{}},
+ {C, 0xff00000000000000, 0x5900000000000000, 0x0, // COMPARE (32) (C R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CR, 0xff00000000000000, 0x1900000000000000, 0x0, // COMPARE (32) (CR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {CY, 0xff00000000ff0000, 0xe300000000590000, 0x0, // COMPARE (32) (CY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CG, 0xff00000000ff0000, 0xe300000000200000, 0x0, // COMPARE (64) (CG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CGR, 0xffff000000000000, 0xb920000000000000, 0xff0000000000, // COMPARE (64) (CGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CGF, 0xff00000000ff0000, 0xe300000000300000, 0x0, // COMPARE (64←32) (CGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CGFR, 0xffff000000000000, 0xb930000000000000, 0xff0000000000, // COMPARE (64←32) (CGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CXBR, 0xffff000000000000, 0xb349000000000000, 0xff0000000000, // COMPARE (extended BFP) (CXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CXTR, 0xffff000000000000, 0xb3ec000000000000, 0xff0000000000, // COMPARE (extended DFP) (CXTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CXR, 0xffff000000000000, 0xb369000000000000, 0xff0000000000, // COMPARE (extended HFP) (CXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CDB, 0xff00000000ff0000, 0xed00000000190000, 0xff000000, // COMPARE (long BFP) (CDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CDBR, 0xffff000000000000, 0xb319000000000000, 0xff0000000000, // COMPARE (long BFP) (CDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CDTR, 0xffff000000000000, 0xb3e4000000000000, 0xff0000000000, // COMPARE (long DFP) (CDTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CD, 0xff00000000000000, 0x6900000000000000, 0x0, // COMPARE (long HFP) (CD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CDR, 0xff00000000000000, 0x2900000000000000, 0x0, // COMPARE (long HFP) (CDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {CEB, 0xff00000000ff0000, 0xed00000000090000, 0xff000000, // COMPARE (short BFP) (CEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CEBR, 0xffff000000000000, 0xb309000000000000, 0xff0000000000, // COMPARE (short BFP) (CEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CE, 0xff00000000000000, 0x7900000000000000, 0x0, // COMPARE (short HFP) (CE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CER, 0xff00000000000000, 0x3900000000000000, 0x0, // COMPARE (short HFP) (CER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {CRB, 0xff00000000ff0000, 0xec00000000f60000, 0xf000000, // COMPARE AND BRANCH (32) (CRB R1,R2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CGRB, 0xff00000000ff0000, 0xec00000000e40000, 0xf000000, // COMPARE AND BRANCH (64) (CGRB R1,R2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CRJ, 0xff00000000ff0000, 0xec00000000760000, 0xf000000, // COMPARE AND BRANCH RELATIVE (32) (CRJ R1,R2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}},
+ {CGRJ, 0xff00000000ff0000, 0xec00000000640000, 0xf000000, // COMPARE AND BRANCH RELATIVE (64) (CGRJ R1,R2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}},
+ {CFC, 0xffff000000000000, 0xb21a000000000000, 0x0, // COMPARE AND FORM CODEWORD (CFC D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CRDTE, 0xffff000000000000, 0xb98f000000000000, 0x0, // COMPARE AND REPLACE DAT TABLE ENTRY (CRDTE R1,R3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {KXBR, 0xffff000000000000, 0xb348000000000000, 0xff0000000000, // COMPARE AND SIGNAL (extended BFP) (KXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {KXTR, 0xffff000000000000, 0xb3e8000000000000, 0xff0000000000, // COMPARE AND SIGNAL (extended DFP) (KXTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {KDB, 0xff00000000ff0000, 0xed00000000180000, 0xff000000, // COMPARE AND SIGNAL (long BFP) (KDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {KDBR, 0xffff000000000000, 0xb318000000000000, 0xff0000000000, // COMPARE AND SIGNAL (long BFP) (KDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {KDTR, 0xffff000000000000, 0xb3e0000000000000, 0xff0000000000, // COMPARE AND SIGNAL (long DFP) (KDTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {KEB, 0xff00000000ff0000, 0xed00000000080000, 0xff000000, // COMPARE AND SIGNAL (short BFP) (KEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {KEBR, 0xffff000000000000, 0xb308000000000000, 0xff0000000000, // COMPARE AND SIGNAL (short BFP) (KEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CS, 0xff00000000000000, 0xba00000000000000, 0x0, // COMPARE AND SWAP (32) (CS R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CSY, 0xff00000000ff0000, 0xeb00000000140000, 0x0, // COMPARE AND SWAP (32) (CSY R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CSG, 0xff00000000ff0000, 0xeb00000000300000, 0x0, // COMPARE AND SWAP (64) (CSG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CSP, 0xffff000000000000, 0xb250000000000000, 0xff0000000000, // COMPARE AND SWAP AND PURGE (32) (CSP R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CSPG, 0xffff000000000000, 0xb98a000000000000, 0xff0000000000, // COMPARE AND SWAP AND PURGE (64) (CSPG R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CSST, 0xff0f000000000000, 0xc802000000000000, 0x0, // COMPARE AND SWAP AND STORE (CSST D1(B1),D2(B2),R3)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_8_11}},
+ {CRT, 0xffff000000000000, 0xb972000000000000, 0xf0000000000, // COMPARE AND TRAP (32) (CRT R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CGRT, 0xffff000000000000, 0xb960000000000000, 0xf0000000000, // COMPARE AND TRAP (64) (CGRT R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CEXTR, 0xffff000000000000, 0xb3fc000000000000, 0xff0000000000, // COMPARE BIASED EXPONENT (extended DFP) (CEXTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CEDTR, 0xffff000000000000, 0xb3f4000000000000, 0xff0000000000, // COMPARE BIASED EXPONENT (long DFP) (CEDTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CP, 0xff00000000000000, 0xf900000000000000, 0x0, // COMPARE DECIMAL (CP D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {CDS, 0xff00000000000000, 0xbb00000000000000, 0x0, // COMPARE DOUBLE AND SWAP (32) (CDS R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CDSY, 0xff00000000ff0000, 0xeb00000000310000, 0x0, // COMPARE DOUBLE AND SWAP (32) (CDSY R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CDSG, 0xff00000000ff0000, 0xeb000000003e0000, 0x0, // COMPARE DOUBLE AND SWAP (64) (CDSG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CH, 0xff00000000000000, 0x4900000000000000, 0x0, // COMPARE HALFWORD (32→16) (CH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CHY, 0xff00000000ff0000, 0xe300000000790000, 0x0, // COMPARE HALFWORD (32→16) (CHY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CGH, 0xff00000000ff0000, 0xe300000000340000, 0x0, // COMPARE HALFWORD (64←16) (CGH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CHHSI, 0xffff000000000000, 0xe554000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (16→16) (CHHSI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}},
+ {CHI, 0xff0f000000000000, 0xa70e000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (32←16) (CHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
+ {CHSI, 0xffff000000000000, 0xe55c000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (32←16) (CHSI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}},
+ {CGHI, 0xff0f000000000000, 0xa70f000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (64←16) (CGHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
+ {CGHSI, 0xffff000000000000, 0xe558000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (64←16) (CGHSI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}},
+ {CHRL, 0xff0f000000000000, 0xc605000000000000, 0x0, // COMPAREHALFWORDRELATIVE LONG (32→16) (CHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CGHRL, 0xff0f000000000000, 0xc604000000000000, 0x0, // COMPAREHALFWORDRELATIVE LONG (64←16) (CGHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CHF, 0xff00000000ff0000, 0xe300000000cd0000, 0x0, // COMPARE HIGH (32) (CHF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CHHR, 0xffff000000000000, 0xb9cd000000000000, 0xff0000000000, // COMPARE HIGH (32) (CHHR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CHLR, 0xffff000000000000, 0xb9dd000000000000, 0xff0000000000, // COMPARE HIGH (32) (CHLR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CFI, 0xff0f000000000000, 0xc20d000000000000, 0x0, // COMPARE IMMEDIATE (32) (CFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
+ {CGFI, 0xff0f000000000000, 0xc20c000000000000, 0x0, // COMPARE IMMEDIATE (64←32) (CGFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
+ {CIB, 0xff00000000ff0000, 0xec00000000fe0000, 0x0, // COMPARE IMMEDIATE AND BRANCH (32←8) (CIB R1,I2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CGIB, 0xff00000000ff0000, 0xec00000000fc0000, 0x0, // COMPARE IMMEDIATE AND BRANCH (64←8) (CGIB R1,I2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CIJ, 0xff00000000ff0000, 0xec000000007e0000, 0x0, // COMPARE IMMEDIATE AND BRANCH RELATIVE(32→8) (CIJ R1,I2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}},
+ {CGIJ, 0xff00000000ff0000, 0xec000000007c0000, 0x0, // COMPARE IMMEDIATE AND BRANCH RELATIVE(64→8) (CGIJ R1,I2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}},
+ {CIT, 0xff00000000ff0000, 0xec00000000720000, 0xf00000f000000, // COMPARE IMMEDIATE AND TRAP (32→16) (CIT R1,I2,M3)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35}},
+ {CGIT, 0xff00000000ff0000, 0xec00000000700000, 0xf00000f000000, // COMPARE IMMEDIATE AND TRAP (64←16) (CGIT R1,I2,M3)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35}},
+ {CIH, 0xff0f000000000000, 0xcc0d000000000000, 0x0, // COMPARE IMMEDIATE HIGH (32) (CIH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
+ {CL, 0xff00000000000000, 0x5500000000000000, 0x0, // COMPARE LOGICAL (32) (CL R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CLR, 0xff00000000000000, 0x1500000000000000, 0x0, // COMPARE LOGICAL (32) (CLR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {CLY, 0xff00000000ff0000, 0xe300000000550000, 0x0, // COMPARE LOGICAL (32) (CLY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CLG, 0xff00000000ff0000, 0xe300000000210000, 0x0, // COMPARE LOGICAL (64) (CLG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CLGR, 0xffff000000000000, 0xb921000000000000, 0xff0000000000, // COMPARE LOGICAL (64) (CLGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CLGF, 0xff00000000ff0000, 0xe300000000310000, 0x0, // COMPARE LOGICAL (64→32) (CLGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CLGFR, 0xffff000000000000, 0xb931000000000000, 0xff0000000000, // COMPARE LOGICAL (64→32) (CLGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CLC, 0xff00000000000000, 0xd500000000000000, 0x0, // COMPARE LOGICAL (character) (CLC D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {CLI, 0xff00000000000000, 0x9500000000000000, 0x0, // COMPARE LOGICAL (immediate) (CLI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {CLIY, 0xff00000000ff0000, 0xeb00000000550000, 0x0, // COMPARE LOGICAL (immediate) (CLIY D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {CLRB, 0xff00000000ff0000, 0xec00000000f70000, 0xf000000, // COMPARE LOGICAL AND BRANCH (32) (CLRB R1,R2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CLGRB, 0xff00000000ff0000, 0xec00000000e50000, 0xf000000, // COMPARE LOGICAL AND BRANCH (64) (CLGRB R1,R2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CLRJ, 0xff00000000ff0000, 0xec00000000770000, 0xf000000, // COMPARE LOGICAL AND BRANCH RELATIVE(32) (CLRJ R1,R2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}},
+ {CLGRJ, 0xff00000000ff0000, 0xec00000000650000, 0xf000000, // COMPARE LOGICAL AND BRANCH RELATIVE(64) (CLGRJ R1,R2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}},
+ {CLRT, 0xffff000000000000, 0xb973000000000000, 0xf0000000000, // COMPARE LOGICAL AND TRAP (32) (CLRT R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CLT, 0xff00000000ff0000, 0xeb00000000230000, 0x0, // COMPARE LOGICAL AND TRAP (32) (CLT R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CLGRT, 0xffff000000000000, 0xb961000000000000, 0xf0000000000, // COMPARE LOGICAL AND TRAP (64) (CLGRT R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CLGT, 0xff00000000ff0000, 0xeb000000002b0000, 0x0, // COMPARE LOGICAL AND TRAP (64) (CLGT R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CLMH, 0xff00000000ff0000, 0xeb00000000200000, 0x0, // COMPARE LOGICAL CHAR. UNDER MASK (high) (CLMH R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CLM, 0xff00000000000000, 0xbd00000000000000, 0x0, // COMPARE LOGICAL CHAR. UNDER MASK (low) (CLM R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CLMY, 0xff00000000ff0000, 0xeb00000000210000, 0x0, // COMPARE LOGICAL CHAR. UNDER MASK (low) (CLMY R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CLHF, 0xff00000000ff0000, 0xe300000000cf0000, 0x0, // COMPARE LOGICAL HIGH (32) (CLHF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CLHHR, 0xffff000000000000, 0xb9cf000000000000, 0xff0000000000, // COMPARE LOGICAL HIGH (32) (CLHHR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CLHLR, 0xffff000000000000, 0xb9df000000000000, 0xff0000000000, // COMPARE LOGICAL HIGH (32) (CLHLR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CLHHSI, 0xffff000000000000, 0xe555000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (16←16) (CLHHSI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}},
+ {CLFI, 0xff0f000000000000, 0xc20f000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (32) (CLFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {CLFHSI, 0xffff000000000000, 0xe55d000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (32←16) (CLFHSI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}},
+ {CLGHSI, 0xffff000000000000, 0xe559000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (64←16) (CLGHSI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}},
+ {CLGFI, 0xff0f000000000000, 0xc20e000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (64←32) (CLGFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {CLIB, 0xff00000000ff0000, 0xec00000000ff0000, 0x0, // COMPARE LOGICAL IMMEDIATE AND BRANCH(32←8) (CLIB R1,I2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CLGIB, 0xff00000000ff0000, 0xec00000000fd0000, 0x0, // COMPARE LOGICAL IMMEDIATE AND BRANCH(64→8) (CLGIB R1,I2,M3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CLIJ, 0xff00000000ff0000, 0xec000000007f0000, 0x0, // COMPARE LOGICAL IMMEDIATE AND BRANCH (CLIJ R1,I2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}},
+ {CLGIJ, 0xff00000000ff0000, 0xec000000007d0000, 0x0, // RELATIVE (32→8)10COMPARE LOGICAL IMMEDIATE AND BRANCH (CLGIJ R1,I2,M3,RI4)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}},
+ {CLFIT, 0xff00000000ff0000, 0xec00000000730000, 0xf00000f000000, // RELATIVE (64→8)COMPARE LOGICAL IMMEDIATE AND TRAP(32→16) (CLFIT R1,I2,M3)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35}},
+ {CLGIT, 0xff00000000ff0000, 0xec00000000710000, 0xf00000f000000, // COMPARE LOGICAL IMMEDIATE AND TRAP(64←16) (CLGIT R1,I2,M3)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35}},
+ {CLIH, 0xff0f000000000000, 0xcc0f000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE HIGH (32) (CLIH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {CLCL, 0xff00000000000000, 0xf00000000000000, 0x0, // COMPARE LOGICAL LONG (CLCL R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {CLCLE, 0xff00000000000000, 0xa900000000000000, 0x0, // COMPARE LOGICAL LONG EXTENDED (CLCLE R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {CLCLU, 0xff00000000ff0000, 0xeb000000008f0000, 0x0, // COMPARE LOGICAL LONG UNICODE (CLCLU R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {CLRL, 0xff0f000000000000, 0xc60f000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (32) (CLRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CLHRL, 0xff0f000000000000, 0xc607000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (32→16) (CLHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CLGRL, 0xff0f000000000000, 0xc60a000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (64) (CLGRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CLGHRL, 0xff0f000000000000, 0xc606000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (64→16) (CLGHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CLGFRL, 0xff0f000000000000, 0xc60e000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (64→32) (CLGFRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CLST, 0xffff000000000000, 0xb25d000000000000, 0xff0000000000, // COMPARE LOGICAL STRING (CLST R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CRL, 0xff0f000000000000, 0xc60d000000000000, 0x0, // COMPARE RELATIVE LONG (32) (CRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CGRL, 0xff0f000000000000, 0xc608000000000000, 0x0, // COMPARE RELATIVE LONG (64) (CGRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CGFRL, 0xff0f000000000000, 0xc60c000000000000, 0x0, // COMPARE RELATIVE LONG (64←32) (CGFRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {CUSE, 0xffff000000000000, 0xb257000000000000, 0xff0000000000, // COMPARE UNTIL SUBSTRING EQUAL (CUSE R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CMPSC, 0xffff000000000000, 0xb263000000000000, 0xff0000000000, // COMPRESSION CALL (CMPSC R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KDSA, 0xffff000000000000, 0xb93a000000000000, 0xff0000000000, // COMPUTE DIGITAL SIGNATURE AUTHENTICATION (KDSA R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KIMD, 0xffff000000000000, 0xb93e000000000000, 0xff0000000000, // COMPUTE INTERMEDIATE MESSAGE DIGEST (KIMD R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KLMD, 0xffff000000000000, 0xb93f000000000000, 0xff0000000000, // COMPUTE LAST MESSAGE DIGEST (KLMD R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {KMAC, 0xffff000000000000, 0xb91e000000000000, 0xff0000000000, // COMPUTE MESSAGE AUTHENTICATION CODE (KMAC R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {THDR, 0xffff000000000000, 0xb359000000000000, 0xff0000000000, // CONVERT BFP TO HFP (long) (THDR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {THDER, 0xffff000000000000, 0xb358000000000000, 0xff0000000000, // CONVERT BFP TO HFP (short to long) (THDER R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {CXFBR, 0xffff000000000000, 0xb396000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to extended BFP) (CXFBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CXFBRA, 0xffff000000000000, 0xb396000000000000, 0x0, // CONVERT FROM FIXED (32 to extended BFP) (CXFBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXFTR, 0xffff000000000000, 0xb959000000000000, 0x0, // CONVERT FROM FIXED (32 to extended DFP) (CXFTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXFR, 0xffff000000000000, 0xb3b6000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to extended HFP) (CXFR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CDFBR, 0xffff000000000000, 0xb395000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to long BFP) (CDFBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CDFBRA, 0xffff000000000000, 0xb395000000000000, 0x0, // CONVERT FROM FIXED (32 to long BFP) (CDFBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDFTR, 0xffff000000000000, 0xb951000000000000, 0x0, // CONVERT FROM FIXED (32 to long DFP) (CDFTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDFR, 0xffff000000000000, 0xb3b5000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to long HFP) (CDFR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CEFBR, 0xffff000000000000, 0xb394000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to short BFP) (CEFBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CEFBRA, 0xffff000000000000, 0xb394000000000000, 0x0, // CONVERT FROM FIXED (32 to short BFP) (CEFBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CEFR, 0xffff000000000000, 0xb3b4000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to short HFP) (CEFR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CXGBR, 0xffff000000000000, 0xb3a6000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to extended BFP) (CXGBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CXGBRA, 0xffff000000000000, 0xb3a6000000000000, 0x0, // CONVERT FROM FIXED (64 to extended BFP) (CXGBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXGTR, 0xffff000000000000, 0xb3f9000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to extended DFP) (CXGTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CXGTRA, 0xffff000000000000, 0xb3f9000000000000, 0x0, // CONVERT FROM FIXED (64 to extended DFP) (CXGTRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXGR, 0xffff000000000000, 0xb3c6000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to extended HFP) (CXGR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CDGBR, 0xffff000000000000, 0xb3a5000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to long BFP) (CDGBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CDGBRA, 0xffff000000000000, 0xb3a5000000000000, 0x0, // CONVERT FROM FIXED (64 to long BFP) (CDGBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDGTR, 0xffff000000000000, 0xb3f1000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to long DFP) (CDGTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CDGTRA, 0xffff000000000000, 0xb3f1000000000000, 0x0, // CONVERT FROM FIXED (64 to long DFP) (CDGTRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDGR, 0xffff000000000000, 0xb3c5000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to long HFP) (CDGR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CEGBR, 0xffff000000000000, 0xb3a4000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to short BFP) (CEGBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CEGBRA, 0xffff000000000000, 0xb3a4000000000000, 0x0, // CONVERT FROM FIXED (64 to short BFP) (CEGBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CEGR, 0xffff000000000000, 0xb3c4000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to short HFP) (CEGR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CXLFBR, 0xffff000000000000, 0xb392000000000000, 0x0, // CONVERT FROM LOGICAL (32 to extended BFP) (CXLFBR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXLFTR, 0xffff000000000000, 0xb95b000000000000, 0x0, // CONVERT FROM LOGICAL (32 to extended DFP) (CXLFTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDLFBR, 0xffff000000000000, 0xb391000000000000, 0x0, // CONVERT FROM LOGICAL (32 to long BFP) (CDLFBR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDLFTR, 0xffff000000000000, 0xb953000000000000, 0x0, // CONVERT FROM LOGICAL (32 to long DFP) (CDLFTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CELFBR, 0xffff000000000000, 0xb390000000000000, 0x0, // CONVERT FROM LOGICAL (32 to short BFP) (CELFBR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXLGBR, 0xffff000000000000, 0xb3a2000000000000, 0x0, // CONVERT FROM LOGICAL (64 to extended BFP) (CXLGBR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXLGTR, 0xffff000000000000, 0xb95a000000000000, 0x0, // CONVERT FROM LOGICAL (64 to extended DFP) (CXLGTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDLGBR, 0xffff000000000000, 0xb3a1000000000000, 0x0, // CONVERT FROM LOGICAL (64 to long BFP) (CDLGBR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CDLGTR, 0xffff000000000000, 0xb952000000000000, 0x0, // CONVERT FROM LOGICAL (64 to long DFP) (CDLGTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CELGBR, 0xffff000000000000, 0xb3a0000000000000, 0x0, // CONVERT FROM LOGICAL (64 to short BFP) (CELGBR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {CXPT, 0xff00000000ff0000, 0xed00000000af0000, 0x0, // CONVERT FROM PACKED (to extended DFP) (CXPT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {CDPT, 0xff00000000ff0000, 0xed00000000ae0000, 0x0, // CONVERT FROM PACKED (to long DFP) (CDPT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {CXSTR, 0xffff000000000000, 0xb3fb000000000000, 0xff0000000000, // CONVERT FROM SIGNED PACKED (128 to extended DFP) (CXSTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CDSTR, 0xffff000000000000, 0xb3f3000000000000, 0xff0000000000, // CONVERT FROM SIGNED PACKED (64 to long DFP) (CDSTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CXUTR, 0xffff000000000000, 0xb3fa000000000000, 0xff0000000000, // CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) (CXUTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CDUTR, 0xffff000000000000, 0xb3f2000000000000, 0xff0000000000, // CONVERT FROM UNSIGNED PACKED (64 to long DFP) (CDUTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {CXZT, 0xff00000000ff0000, 0xed00000000ab0000, 0x0, // CONVERT FROM ZONED (to extended DFP) (CXZT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {CDZT, 0xff00000000ff0000, 0xed00000000aa0000, 0x0, // CONVERT FROM ZONED (to long DFP) (CDZT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {TBEDR, 0xffff000000000000, 0xb350000000000000, 0xf0000000000, // CONVERT HFP TO BFP (long to short) (TBEDR R1,M3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {TBDR, 0xffff000000000000, 0xb351000000000000, 0xf0000000000, // CONVERT HFP TO BFP (long) (TBDR R1,M3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CVB, 0xff00000000000000, 0x4f00000000000000, 0x0, // CONVERT TO BINARY (32) (CVB R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CVBY, 0xff00000000ff0000, 0xe300000000060000, 0x0, // CONVERT TO BINARY (32) (CVBY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CVBG, 0xff00000000ff0000, 0xe3000000000e0000, 0x0, // CONVERT TO BINARY (64) (CVBG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CVD, 0xff00000000000000, 0x4e00000000000000, 0x0, // CONVERT TO DECIMAL (32) (CVD R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CVDY, 0xff00000000ff0000, 0xe300000000260000, 0x0, // CONVERT TO DECIMAL (32) (CVDY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CVDG, 0xff00000000ff0000, 0xe3000000002e0000, 0x0, // CONVERT TO DECIMAL (64) (CVDG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {CFXBR, 0xffff000000000000, 0xb39a000000000000, 0xf0000000000, // CONVERT TO FIXED (extended BFP to 32) (CFXBR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CFXBRA, 0xffff000000000000, 0xb39a000000000000, 0x0, // CONVERT TO FIXED (extended BFP to 32) (CFXBRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CGXBR, 0xffff000000000000, 0xb3aa000000000000, 0xf0000000000, // CONVERT TO FIXED (extended BFP to 64) (CGXBR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGXBRA, 0xffff000000000000, 0xb3aa000000000000, 0x0, // CONVERT TO FIXED (extended BFP to 64) (CGXBRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CFXTR, 0xffff000000000000, 0xb949000000000000, 0x0, // CONVERT TO FIXED (extended DFP to 32) (CFXTR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CGXTR, 0xffff000000000000, 0xb3e9000000000000, 0xf0000000000, // CONVERT TO FIXED (extended DFP to 64) (CGXTR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGXTRA, 0xffff000000000000, 0xb3e9000000000000, 0x0, // CONVERT TO FIXED (extended DFP to 64) (CGXTRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CFXR, 0xffff000000000000, 0xb3ba000000000000, 0xf0000000000, // CONVERT TO FIXED (extended HFP to 32) (CFXR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGXR, 0xffff000000000000, 0xb3ca000000000000, 0xf0000000000, // CONVERT TO FIXED (extended HFP to 64) (CGXR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CFDBR, 0xffff000000000000, 0xb399000000000000, 0xf0000000000, // CONVERT TO FIXED (long BFP to 32) (CFDBR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CFDBRA, 0xffff000000000000, 0xb399000000000000, 0x0, // CONVERT TO FIXED (long BFP to 32) (CFDBRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CGDBR, 0xffff000000000000, 0xb3a9000000000000, 0xf0000000000, // CONVERT TO FIXED (long BFP to 64) (CGDBR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGDBRA, 0xffff000000000000, 0xb3a9000000000000, 0x0, // CONVERT TO FIXED (long BFP to 64) (CGDBRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CFDTR, 0xffff000000000000, 0xb941000000000000, 0x0, // CONVERT TO FIXED (long DFP to 32) (CFDTR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CGDTR, 0xffff000000000000, 0xb3e1000000000000, 0xf0000000000, // CONVERT TO FIXED (long DFP to 64) (CGDTR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGDTRA, 0xffff000000000000, 0xb3e1000000000000, 0x0, // CONVERT TO FIXED (long DFP to 64) (CGDTRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CFDR, 0xffff000000000000, 0xb3b9000000000000, 0xf0000000000, // CONVERT TO FIXED (long HFP to 32) (CFDR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGDR, 0xffff000000000000, 0xb3c9000000000000, 0xf0000000000, // CONVERT TO FIXED (long HFP to 64) (CGDR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CFEBR, 0xffff000000000000, 0xb398000000000000, 0xf0000000000, // CONVERT TO FIXED (short BFP to 32) (CFEBR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CFEBRA, 0xffff000000000000, 0xb398000000000000, 0x0, // CONVERT TO FIXED (short BFP to 32) (CFEBRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CGEBR, 0xffff000000000000, 0xb3a8000000000000, 0xf0000000000, // CONVERT TO FIXED (short BFP to 64) (CGEBR R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGEBRA, 0xffff000000000000, 0xb3a8000000000000, 0x0, // CONVERT TO FIXED (short BFP to 64) (CGEBRA R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CFER, 0xffff000000000000, 0xb3b8000000000000, 0xf0000000000, // CONVERT TO FIXED (short HFP to 32) (CFER R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CGER, 0xffff000000000000, 0xb3c8000000000000, 0xf0000000000, // CONVERT TO FIXED (short HFP to 64) (CGER R1,M3,R2)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {CLFXBR, 0xffff000000000000, 0xb39e000000000000, 0x0, // CONVERT TO LOGICAL (extended BFP to 32) (CLFXBR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLGXBR, 0xffff000000000000, 0xb3ae000000000000, 0x0, // CONVERT TO LOGICAL (extended BFP to 64) (CLGXBR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLFXTR, 0xffff000000000000, 0xb94b000000000000, 0x0, // CONVERT TO LOGICAL (extended DFP to 32) (CLFXTR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLGXTR, 0xffff000000000000, 0xb94a000000000000, 0x0, // CONVERT TO LOGICAL (extended DFP to 64) (CLGXTR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLFDBR, 0xffff000000000000, 0xb39d000000000000, 0x0, // CONVERT TO LOGICAL (long BFP to 32) (CLFDBR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLGDBR, 0xffff000000000000, 0xb3ad000000000000, 0x0, // CONVERT TO LOGICAL (long BFP to 64) (CLGDBR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLFDTR, 0xffff000000000000, 0xb943000000000000, 0x0, // CONVERT TO LOGICAL (long DFP to 32) (CLFDTR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLGDTR, 0xffff000000000000, 0xb942000000000000, 0x0, // CONVERT TO LOGICAL (long DFP to 64) (CLGDTR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLFEBR, 0xffff000000000000, 0xb39c000000000000, 0x0, // CONVERT TO LOGICAL (short BFP to 32) (CLFEBR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CLGEBR, 0xffff000000000000, 0xb3ac000000000000, 0x0, // CONVERT TO LOGICAL (short BFP to 64) (CLGEBR R1,M3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CPXT, 0xff00000000ff0000, 0xed00000000ad0000, 0x0, // CONVERT TO PACKED (from extended DFP) (CPXT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {CPDT, 0xff00000000ff0000, 0xed00000000ac0000, 0x0, // CONVERT TO PACKED (from long DFP) (CPDT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {CSXTR, 0xffff000000000000, 0xb3eb000000000000, 0xf00000000000, // CONVERT TO SIGNED PACKED (extended DFP to 128) (CSXTR R1,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CSDTR, 0xffff000000000000, 0xb3e3000000000000, 0xf00000000000, // CONVERT TO SIGNED PACKED (long DFP to 64) (CSDTR R1,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31, ap_Mask_20_23}},
+ {CUXTR, 0xffff000000000000, 0xb3ea000000000000, 0xff0000000000, // CONVERTTOUNSIGNEDPACKED(extendedDFP to 128) (CUXTR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}},
+ {CUDTR, 0xffff000000000000, 0xb3e2000000000000, 0xff0000000000, // CONVERT TO UNSIGNED PACKED (long DFP to 64) (CUDTR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}},
+ {CZXT, 0xff00000000ff0000, 0xed00000000a90000, 0x0, // CONVERT TO ZONED (from extended DFP) (CZXT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {CZDT, 0xff00000000ff0000, 0xed00000000a80000, 0x0, // CONVERT TO ZONED (from long DFP) (CZDT R1,D2(L2,B2),M3)
+ [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}},
+ {CU24, 0xffff000000000000, 0xb9b1000000000000, 0xf0000000000, // CONVERT UTF-16 TO UTF-32 (CU24 R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CU21, 0xffff000000000000, 0xb2a6000000000000, 0xf0000000000, // CONVERT UTF-16 TO UTF-8 (CU21 R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CU12, 0xffff000000000000, 0xb2a7000000000000, 0xf0000000000, // CONVERT UTF-8 TO UTF-16 (CU12 R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CU14, 0xffff000000000000, 0xb9b0000000000000, 0xf0000000000, // CONVERT UTF-8 TO UTF-32 (CU14 R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {CU42, 0xffff000000000000, 0xb9b3000000000000, 0xff0000000000, // CONVERT UTF-32 TO UTF-16 (CU42 R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CU41, 0xffff000000000000, 0xb9b2000000000000, 0xff0000000000, // CONVERT UTF-32 TO UTF-8 (CU41 R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {CPYA, 0xffff000000000000, 0xb24d000000000000, 0xff0000000000, // COPY ACCESS (CPYA R1,R2)
+ [8]*argField{ap_ACReg_24_27, ap_ACReg_28_31}},
+ {CPSDR, 0xffff000000000000, 0xb372000000000000, 0xf0000000000, // COPY SIGN (long) (CPSDR R1,R3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31}},
+ {VSCSHP, 0xff00000000ff0000, 0xe6000000007c0000, 0xffff0000000, // DECIMAL SCALE AND CONVERT AND SPLIT TO HFP (VSCSHP V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSCHP, 0xff00000000ff0000, 0xe600000000740000, 0xf0f00000000, // DECIMAL SCALE AND CONVERT TO HFP (VSCHP V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {DFLTCC, 0xffff000000000000, 0xb939000000000000, 0xf0000000000, // DEFLATE CONVERSION CALL (DFLTCC R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {D, 0xff00000000000000, 0x5d00000000000000, 0x0, // DIVIDE (32→64) (D R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DR, 0xff00000000000000, 0x1d00000000000000, 0x0, // DIVIDE (32←64) (DR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {DXBR, 0xffff000000000000, 0xb34d000000000000, 0xff0000000000, // DIVIDE (extended BFP) (DXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {DXTR, 0xffff000000000000, 0xb3d9000000000000, 0xf0000000000, // DIVIDE (extended DFP) (DXTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {DXTRA, 0xffff000000000000, 0xb3d9000000000000, 0x0, // DIVIDE (extended DFP) (DXTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {DXR, 0xffff000000000000, 0xb22d000000000000, 0xff0000000000, // DIVIDE (extended HFP) (DXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {DDB, 0xff00000000ff0000, 0xed000000001d0000, 0xff000000, // DIVIDE (long BFP) (DDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DDBR, 0xffff000000000000, 0xb31d000000000000, 0xff0000000000, // DIVIDE (long BFP) (DDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {DDTR, 0xffff000000000000, 0xb3d1000000000000, 0xf0000000000, // DIVIDE (long DFP) (DDTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {DDTRA, 0xffff000000000000, 0xb3d1000000000000, 0x0, // DIVIDE (long DFP) (DDTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {DD, 0xff00000000000000, 0x6d00000000000000, 0x0, // DIVIDE (long HFP) (DD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DDR, 0xff00000000000000, 0x2d00000000000000, 0x0, // DIVIDE (long HFP) (DDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {DEB, 0xff00000000ff0000, 0xed000000000d0000, 0xff000000, // DIVIDE (short BFP) (DEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DEBR, 0xffff000000000000, 0xb30d000000000000, 0xff0000000000, // DIVIDE (short BFP) (DEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {DE, 0xff00000000000000, 0x7d00000000000000, 0x0, // DIVIDE (short HFP) (DE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DER, 0xff00000000000000, 0x3d00000000000000, 0x0, // DIVIDE (short HFP) (DER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {DP, 0xff00000000000000, 0xfd00000000000000, 0x0, // DIVIDE DECIMAL (DP D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {DL, 0xff00000000ff0000, 0xe300000000970000, 0x0, // DIVIDE LOGICAL (32→64) (DL R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DLR, 0xffff000000000000, 0xb997000000000000, 0xff0000000000, // DIVIDE LOGICAL (32←64) (DLR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {DLG, 0xff00000000ff0000, 0xe300000000870000, 0x0, // DIVIDE LOGICAL (64←128) (DLG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DLGR, 0xffff000000000000, 0xb987000000000000, 0xff0000000000, // DIVIDE LOGICAL (64→128) (DLGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {DSG, 0xff00000000ff0000, 0xe3000000000d0000, 0x0, // DIVIDE SINGLE (64) (DSG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DSGR, 0xffff000000000000, 0xb90d000000000000, 0xff0000000000, // DIVIDE SINGLE (64) (DSGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {DSGF, 0xff00000000ff0000, 0xe3000000001d0000, 0x0, // DIVIDE SINGLE (64←32) (DSGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {DSGFR, 0xffff000000000000, 0xb91d000000000000, 0xff0000000000, // DIVIDE SINGLE (64→32) (DSGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {DIDBR, 0xffff000000000000, 0xb35b000000000000, 0x0, // DIVIDE TO INTEGER (long BFP) (DIDBR R1,R3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {DIEBR, 0xffff000000000000, 0xb353000000000000, 0x0, // DIVIDE TO INTEGER (short BFP) (DIEBR R1,R3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {ED, 0xff00000000000000, 0xde00000000000000, 0x0, // EDIT (ED D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {EDMK, 0xff00000000000000, 0xdf00000000000000, 0x0, // EDIT AND MARK (EDMK D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {X, 0xff00000000000000, 0x5700000000000000, 0x0, // EXCLUSIVE OR (32) (X R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {XR, 0xff00000000000000, 0x1700000000000000, 0x0, // EXCLUSIVE OR (32) (XR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {XRK, 0xffff000000000000, 0xb9f7000000000000, 0xf0000000000, // EXCLUSIVE OR (32) (XRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {XY, 0xff00000000ff0000, 0xe300000000570000, 0x0, // EXCLUSIVE OR (32) (XY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {XG, 0xff00000000ff0000, 0xe300000000820000, 0x0, // EXCLUSIVE OR (64) (XG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {XGR, 0xffff000000000000, 0xb982000000000000, 0xff0000000000, // EXCLUSIVE OR (64) (XGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {XGRK, 0xffff000000000000, 0xb9e7000000000000, 0xf0000000000, // EXCLUSIVE OR (64) (XGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {XC, 0xff00000000000000, 0xd700000000000000, 0x0, // EXCLUSIVE OR (character) (XC D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {XI, 0xff00000000000000, 0x9700000000000000, 0x0, // EXCLUSIVE OR (immediate) (XI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {XIY, 0xff00000000ff0000, 0xeb00000000570000, 0x0, // EXCLUSIVE OR (immediate) (XIY D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {XIHF, 0xff0f000000000000, 0xc006000000000000, 0x0, // EXCLUSIVE OR IMMEDIATE (high) (XIHF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {XILF, 0xff0f000000000000, 0xc007000000000000, 0x0, // EXCLUSIVE OR IMMEDIATE (low) (XILF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {EX, 0xff00000000000000, 0x4400000000000000, 0x0, // EXECUTE (EX R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {EXRL, 0xff0f000000000000, 0xc600000000000000, 0x0, // EXECUTE RELATIVE LONG (EXRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {EAR, 0xffff000000000000, 0xb24f000000000000, 0xff0000000000, // EXTRACT ACCESS (EAR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_ACReg_28_31}},
+ {ESEA, 0xffff000000000000, 0xb99d000000000000, 0xff0f00000000, // EXTRACT AND SET EXTENDED AUTHORITY (ESEA R1)
+ [8]*argField{ap_Reg_24_27}},
+ {EEXTR, 0xffff000000000000, 0xb3ed000000000000, 0xff0000000000, // EXTRACT BIASED EXPONENT (extended DFP to 64) (EEXTR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}},
+ {EEDTR, 0xffff000000000000, 0xb3e5000000000000, 0xff0000000000, // EXTRACT BIASED EXPONENT (long DFP to 64) (EEDTR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}},
+ {ECAG, 0xff00000000ff0000, 0xeb000000004c0000, 0x0, // EXTRACT CPU ATTRIBUTE (ECAG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {ECTG, 0xff0f000000000000, 0xc801000000000000, 0x0, // EXTRACT CPU TIME (ECTG D1(B1),D2(B2),R3)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_8_11}},
+ {EFPC, 0xffff000000000000, 0xb38c000000000000, 0xff0f00000000, // EXTRACT FPC (EFPC R1)
+ [8]*argField{ap_Reg_24_27}},
+ {EPAR, 0xffff000000000000, 0xb226000000000000, 0xff0f00000000, // EXTRACT PRIMARY ASN (EPAR R1)
+ [8]*argField{ap_Reg_24_27}},
+ {EPAIR, 0xffff000000000000, 0xb99a000000000000, 0xff0f00000000, // EXTRACT PRIMARY ASN AND INSTANCE (EPAIR R1)
+ [8]*argField{ap_Reg_24_27}},
+ {EPSW, 0xffff000000000000, 0xb98d000000000000, 0xff0000000000, // EXTRACT PSW (EPSW R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ESAR, 0xffff000000000000, 0xb227000000000000, 0xff0f00000000, // EXTRACT SECONDARY ASN (ESAR R1)
+ [8]*argField{ap_Reg_24_27}},
+ {ESAIR, 0xffff000000000000, 0xb99b000000000000, 0xff0f00000000, // EXTRACT SECONDARY ASN AND INSTANCE (ESAIR R1)
+ [8]*argField{ap_Reg_24_27}},
+ {ESXTR, 0xffff000000000000, 0xb3ef000000000000, 0xff0000000000, // EXTRACT SIGNIFICANCE (extended DFP to 64) (ESXTR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}},
+ {ESDTR, 0xffff000000000000, 0xb3e7000000000000, 0xff0000000000, // EXTRACT SIGNIFICANCE (long DFP to 64) (ESDTR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}},
+ {EREG, 0xffff000000000000, 0xb249000000000000, 0xff0000000000, // EXTRACT STACKED REGISTERS (32) (EREG R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {EREGG, 0xffff000000000000, 0xb90e000000000000, 0xff0000000000, // EXTRACT STACKED REGISTERS (64) (EREGG R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ESTA, 0xffff000000000000, 0xb24a000000000000, 0xff0000000000, // EXTRACT STACKED STATE (ESTA R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ETND, 0xffff000000000000, 0xb2ec000000000000, 0xff0f00000000, // EXTRACT TRANSACTION NESTING DEPTH (ETND R1)
+ [8]*argField{ap_Reg_24_27}},
+ {FLOGR, 0xffff000000000000, 0xb983000000000000, 0xff0000000000, // FIND LEFTMOST ONE (FLOGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {HSCH, 0xffff000000000000, 0xb231000000000000, 0xffff00000000, // HALT SUBCHANNEL (HSCH)
+ [8]*argField{}},
+ {HDR, 0xff00000000000000, 0x2400000000000000, 0x0, // HALVE (long HFP) (HDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {HER, 0xff00000000000000, 0x3400000000000000, 0x0, // HALVE (short HFP) (HER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {IAC, 0xffff000000000000, 0xb224000000000000, 0xff0f00000000, // INSERT ADDRESS SPACE CONTROL (IAC R1)
+ [8]*argField{ap_Reg_24_27}},
+ {IEXTR, 0xffff000000000000, 0xb3fe000000000000, 0xf0000000000, // INSERT BIASED EXPONENT (64 to extended DFP) (IEXTR R1,R3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31}},
+ {IEDTR, 0xffff000000000000, 0xb3f6000000000000, 0xf0000000000, // INSERT BIASED EXPONENT (64 to long DFP) (IEDTR R1,R3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31}},
+ {IC, 0xff00000000000000, 0x4300000000000000, 0x0, // INSERT CHARACTER (IC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ICY, 0xff00000000ff0000, 0xe300000000730000, 0x0, // INSERT CHARACTER (ICY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {ICMH, 0xff00000000ff0000, 0xeb00000000800000, 0x0, // INSERT CHARACTERS UNDER MASK (high) (ICMH R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {ICM, 0xff00000000000000, 0xbf00000000000000, 0x0, // INSERT CHARACTERS UNDER MASK (low) (ICM R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {ICMY, 0xff00000000ff0000, 0xeb00000000810000, 0x0, // INSERT CHARACTERS UNDER MASK (low) (ICMY R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {IIHH, 0xff0f000000000000, 0xa500000000000000, 0x0, // INSERT IMMEDIATE (high high) (IIHH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {IIHL, 0xff0f000000000000, 0xa501000000000000, 0x0, // INSERT IMMEDIATE (high low) (IIHL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {IIHF, 0xff0f000000000000, 0xc008000000000000, 0x0, // INSERT IMMEDIATE (high) (IIHF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {IILH, 0xff0f000000000000, 0xa502000000000000, 0x0, // INSERT IMMEDIATE (low high) (IILH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {IILL, 0xff0f000000000000, 0xa503000000000000, 0x0, // INSERT IMMEDIATE (low low) (IILL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {IILF, 0xff0f000000000000, 0xc009000000000000, 0x0, // INSERT IMMEDIATE (low) (IILF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {IPM, 0xffff000000000000, 0xb222000000000000, 0xff0f00000000, // INSERT PROGRAM MASK (IPM R1)
+ [8]*argField{ap_Reg_24_27}},
+ {IPK, 0xffff000000000000, 0xb20b000000000000, 0xffff00000000, // INSERT PSW KEY (IPK)
+ [8]*argField{}},
+ {IRBM, 0xffff000000000000, 0xb9ac000000000000, 0xff0000000000, // INSERT REFERENCE BITS MULTIPLE (IRBM R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ISKE, 0xffff000000000000, 0xb229000000000000, 0xff0000000000, // INSERT STORAGE KEY EXTENDED (ISKE R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {IVSK, 0xffff000000000000, 0xb223000000000000, 0xff0000000000, // INSERT VIRTUAL STORAGE KEY (IVSK R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {IDTE, 0xffff000000000000, 0xb98e000000000000, 0x0, // INVALIDATE DAT TABLE ENTRY (IDTE R1,R3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {IPTE, 0xffff000000000000, 0xb221000000000000, 0x0, // INVALIDATE PAGE TABLE ENTRY (IPTE R1,R2,R3,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}},
+ {L, 0xff00000000000000, 0x5800000000000000, 0x0, // LOAD (32) (L R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LR, 0xff00000000000000, 0x1800000000000000, 0x0, // LOAD (32) (LR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {LY, 0xff00000000ff0000, 0xe300000000580000, 0x0, // LOAD (32) (LY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LG, 0xff00000000ff0000, 0xe300000000040000, 0x0, // LOAD (64) (LG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LGR, 0xffff000000000000, 0xb904000000000000, 0xff0000000000, // LOAD (64) (LGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LGF, 0xff00000000ff0000, 0xe300000000140000, 0x0, // LOAD (64←32) (LGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LGFR, 0xffff000000000000, 0xb914000000000000, 0xff0000000000, // LOAD (64←32) (LGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LXR, 0xffff000000000000, 0xb365000000000000, 0xff0000000000, // LOAD (extended) (LXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LD, 0xff00000000000000, 0x6800000000000000, 0x0, // LOAD (long) (LD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LDR, 0xff00000000000000, 0x2800000000000000, 0x0, // LOAD (long) (LDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LDY, 0xff00000000ff0000, 0xed00000000650000, 0x0, // LOAD (long) (LDY R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LE, 0xff00000000000000, 0x7800000000000000, 0x0, // LOAD (short) (LE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LER, 0xff00000000000000, 0x3800000000000000, 0x0, // LOAD (short) (LER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LEY, 0xff00000000ff0000, 0xed00000000640000, 0x0, // LOAD (short) (LEY R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LAM, 0xff00000000000000, 0x9a00000000000000, 0x0, // LOAD ACCESS MULTIPLE 7-268 (LAM R1,R3,D2(B2))
+ [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LAMY, 0xff00000000ff0000, 0xeb000000009a0000, 0x0, // LOAD ACCESS MULTIPLE 7-268 (LAMY R1,R3,D2(B2))
+ [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LA, 0xff00000000000000, 0x4100000000000000, 0x0, // LOAD ADDRESS (LA R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LAY, 0xff00000000ff0000, 0xe300000000710000, 0x0, // LOAD ADDRESS (LAY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LAE, 0xff00000000000000, 0x5100000000000000, 0x0, // LOAD ADDRESS EXTENDED (LAE R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LAEY, 0xff00000000ff0000, 0xe300000000750000, 0x0, // LOAD ADDRESS EXTENDED (LAEY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LARL, 0xff0f000000000000, 0xc000000000000000, 0x0, // LOAD ADDRESS RELATIVE LONG (LARL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LASP, 0xffff000000000000, 0xe500000000000000, 0x0, // LOAD ADDRESS SPACE PARAMETERS (LASP D1(B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {LAA, 0xff00000000ff0000, 0xeb00000000f80000, 0x0, // LOAD AND ADD (32) (LAA R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAAG, 0xff00000000ff0000, 0xeb00000000e80000, 0x0, // LOAD AND ADD (64) (LAAG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAAL, 0xff00000000ff0000, 0xeb00000000fa0000, 0x0, // LOAD AND ADD LOGICAL (32) (LAAL R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAALG, 0xff00000000ff0000, 0xeb00000000ea0000, 0x0, // LOAD AND ADD LOGICAL (64) (LAALG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAN, 0xff00000000ff0000, 0xeb00000000f40000, 0x0, // LOAD AND AND (32) (LAN R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LANG, 0xff00000000ff0000, 0xeb00000000e40000, 0x0, // LOAD AND AND (64) (LANG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAX, 0xff00000000ff0000, 0xeb00000000f70000, 0x0, // LOAD AND EXCLUSIVE OR (32) (LAX R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAXG, 0xff00000000ff0000, 0xeb00000000e70000, 0x0, // LOAD AND EXCLUSIVE OR (64) (LAXG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAO, 0xff00000000ff0000, 0xeb00000000f60000, 0x0, // LOAD AND OR (32) (LAO R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LAOG, 0xff00000000ff0000, 0xeb00000000e60000, 0x0, // LOAD AND OR (64) (LAOG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LT, 0xff00000000ff0000, 0xe300000000120000, 0x0, // LOAD AND TEST (32) (LT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LTR, 0xff00000000000000, 0x1200000000000000, 0x0, // LOAD AND TEST (32) (LTR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {LTG, 0xff00000000ff0000, 0xe300000000020000, 0x0, // LOAD AND TEST (64) (LTG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LTGR, 0xffff000000000000, 0xb902000000000000, 0xff0000000000, // LOAD AND TEST (64) (LTGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LTGF, 0xff00000000ff0000, 0xe300000000320000, 0x0, // LOAD AND TEST (64→32) (LTGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LTGFR, 0xffff000000000000, 0xb912000000000000, 0xff0000000000, // LOAD AND TEST (64→32) (LTGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LTXBR, 0xffff000000000000, 0xb342000000000000, 0xff0000000000, // LOAD AND TEST (extended BFP) (LTXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LTXTR, 0xffff000000000000, 0xb3de000000000000, 0xff0000000000, // LOAD AND TEST (extended DFP) (LTXTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LTXR, 0xffff000000000000, 0xb362000000000000, 0xff0000000000, // LOAD AND TEST (extended HFP) (LTXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LTDBR, 0xffff000000000000, 0xb312000000000000, 0xff0000000000, // LOAD AND TEST (long BFP) (LTDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LTDTR, 0xffff000000000000, 0xb3d6000000000000, 0xff0000000000, // LOAD AND TEST (long DFP) (LTDTR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LTDR, 0xff00000000000000, 0x2200000000000000, 0x0, // LOAD AND TEST (long HFP) (LTDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LTEBR, 0xffff000000000000, 0xb302000000000000, 0xff0000000000, // LOAD AND TEST (short BFP) (LTEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LTER, 0xff00000000000000, 0x3200000000000000, 0x0, // LOAD AND TEST (short HFP) (LTER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LAT, 0xff00000000ff0000, 0xe3000000009f0000, 0x0, // LOAD AND TRAP (32L→32) (LAT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LGAT, 0xff00000000ff0000, 0xe300000000850000, 0x0, // LOAD AND TRAP (64) (LGAT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LZRF, 0xff00000000ff0000, 0xe3000000003b0000, 0x0, // LOAD AND ZERO RIGHTMOST BYTE (32) (LZRF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LZRG, 0xff00000000ff0000, 0xe3000000002a0000, 0x0, // LOAD AND ZERO RIGHTMOST BYTE (64) (LZRG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LBEAR, 0xffff000000000000, 0xb200000000000000, 0x0, // LOAD BEAR (LBEAR D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LB, 0xff00000000ff0000, 0xe300000000760000, 0x0, // LOAD BYTE (32→8) (LB R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LBR, 0xffff000000000000, 0xb926000000000000, 0xff0000000000, // LOAD BYTE (32←8) (LBR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LGB, 0xff00000000ff0000, 0xe300000000770000, 0x0, // LOAD BYTE (64→8) (LGB R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LGBR, 0xffff000000000000, 0xb906000000000000, 0xff0000000000, // LOAD BYTE (64←8) (LGBR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LBH, 0xff00000000ff0000, 0xe300000000c00000, 0x0, // LOAD BYTE HIGH (32←8) (LBH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LCR, 0xff00000000000000, 0x1300000000000000, 0x0, // LOAD COMPLEMENT (32) (LCR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {LCGR, 0xffff000000000000, 0xb903000000000000, 0xff0000000000, // LOAD COMPLEMENT (64) (LCGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LCGFR, 0xffff000000000000, 0xb913000000000000, 0xff0000000000, // LOAD COMPLEMENT (64←32) (LCGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LCXBR, 0xffff000000000000, 0xb343000000000000, 0xff0000000000, // LOAD COMPLEMENT (extended BFP) (LCXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LCXR, 0xffff000000000000, 0xb363000000000000, 0xff0000000000, // LOAD COMPLEMENT (extended HFP) (LCXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LCDBR, 0xffff000000000000, 0xb313000000000000, 0xff0000000000, // LOAD COMPLEMENT (long BFP) (LCDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LCDR, 0xff00000000000000, 0x2300000000000000, 0x0, // LOAD COMPLEMENT (long HFP) (LCDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LCDFR, 0xffff000000000000, 0xb373000000000000, 0xff0000000000, // LOAD COMPLEMENT (long) (LCDFR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LCEBR, 0xffff000000000000, 0xb303000000000000, 0xff0000000000, // LOAD COMPLEMENT (short BFP) (LCEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LCER, 0xff00000000000000, 0x3300000000000000, 0x0, // LOAD COMPLEMENT (short HFP) (LCER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LCTL, 0xff00000000000000, 0xb700000000000000, 0x0, // LOAD CONTROL (32) (LCTL R1,R3,D2(B2))
+ [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LCTLG, 0xff00000000ff0000, 0xeb000000002f0000, 0x0, // LOAD CONTROL (64) (LCTLG R1,R3,D2(B2))
+ [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LCBB, 0xff00000000ff0000, 0xe700000000270000, 0xf000000, // LOAD COUNT TO BLOCK BOUNDARY (LCBB R1,D2(X2,B2),M3)
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35}},
+ {FIXBR, 0xffff000000000000, 0xb347000000000000, 0xf0000000000, // LOAD FP INTEGER (extended BFP) (FIXBR R1,M3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {FIXBRA, 0xffff000000000000, 0xb347000000000000, 0x0, // LOAD FP INTEGER (extended BFP) (FIXBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {FIXTR, 0xffff000000000000, 0xb3df000000000000, 0x0, // LOAD FP INTEGER (extended DFP) (FIXTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {FIXR, 0xffff000000000000, 0xb367000000000000, 0xff0000000000, // LOAD FP INTEGER (extended HFP) (FIXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {FIDBR, 0xffff000000000000, 0xb35f000000000000, 0xf0000000000, // LOAD FP INTEGER (long BFP) (FIDBR R1,M3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {FIDBRA, 0xffff000000000000, 0xb35f000000000000, 0x0, // LOAD FP INTEGER (long BFP) (FIDBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {FIDTR, 0xffff000000000000, 0xb3d7000000000000, 0x0, // LOAD FP INTEGER (long DFP) (FIDTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {FIDR, 0xffff000000000000, 0xb37f000000000000, 0xff0000000000, // LOAD FP INTEGER (long HFP) (FIDR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {FIEBR, 0xffff000000000000, 0xb357000000000000, 0xf0000000000, // LOAD FP INTEGER (short BFP) (FIEBR R1,M3,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}},
+ {FIEBRA, 0xffff000000000000, 0xb357000000000000, 0x0, // LOAD FP INTEGER (short BFP) (FIEBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {FIER, 0xffff000000000000, 0xb377000000000000, 0xff0000000000, // LOAD FP INTEGER (short HFP) (FIER R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LFPC, 0xffff000000000000, 0xb29d000000000000, 0x0, // LOAD FPC (LFPC D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LFAS, 0xffff000000000000, 0xb2bd000000000000, 0x0, // LOAD FPC AND SIGNAL (LFAS D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LDGR, 0xffff000000000000, 0xb3c1000000000000, 0xff0000000000, // LOAD FPR FROM GR (64 to long) (LDGR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}},
+ {LGDR, 0xffff000000000000, 0xb3cd000000000000, 0xff0000000000, // LOAD GR FROM FPR (long to 64) (LGDR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}},
+ {LGG, 0xff00000000ff0000, 0xe3000000004c0000, 0x0, // LOAD GUARDED (64) (LGG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LGSC, 0xff00000000ff0000, 0xe3000000004d0000, 0x0, // LOAD GUARDED STORAGE CONTROLS (LGSC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LH, 0xff00000000000000, 0x4800000000000000, 0x0, // LOAD HALFWORD (32→16) (LH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LHR, 0xffff000000000000, 0xb927000000000000, 0xff0000000000, // LOAD HALFWORD (32←16) (LHR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LHY, 0xff00000000ff0000, 0xe300000000780000, 0x0, // LOAD HALFWORD (32←16) (LHY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LGH, 0xff00000000ff0000, 0xe300000000150000, 0x0, // LOAD HALFWORD (64←16) (LGH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LGHR, 0xffff000000000000, 0xb907000000000000, 0xff0000000000, // LOAD HALFWORD (64←16) (LGHR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LHH, 0xff00000000ff0000, 0xe300000000c40000, 0x0, // LOAD HALFWORD HIGH (32→16) (LHH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LOCHHI, 0xff00000000ff0000, 0xec000000004e0000, 0xff000000, // LOAD HALFWORD HIGH IMMEDIATE ON (LOCHHI R1,I2,M3)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_12_15}},
+ {LHI, 0xff0f000000000000, 0xa708000000000000, 0x0, // CONDITION (32←16)LOAD HALFWORD IMMEDIATE (32)←16 (LHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
+ {LGHI, 0xff0f000000000000, 0xa709000000000000, 0x0, // LOAD HALFWORD IMMEDIATE (64→16) (LGHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
+ {LOCHI, 0xff00000000ff0000, 0xec00000000420000, 0xff000000, // LOAD HALFWORD IMMEDIATE ON CONDITION(32←16) (LOCHI R1,I2,M3)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_12_15}},
+ {LOCGHI, 0xff00000000ff0000, 0xec00000000460000, 0xff000000, // LOAD HALFWORD IMMEDIATE ON CONDITION(64→16) (LOCGHI R1,I2,M3)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_12_15}},
+ {LHRL, 0xff0f000000000000, 0xc405000000000000, 0x0, // LOAD HALFWORD RELATIVE LONG (32←16) (LHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LGHRL, 0xff0f000000000000, 0xc404000000000000, 0x0, // LOAD HALFWORD RELATIVE LONG (64←16) (LGHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LFH, 0xff00000000ff0000, 0xe300000000ca0000, 0x0, // LOAD HIGH (32) (LFH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LFHAT, 0xff00000000ff0000, 0xe300000000c80000, 0x0, // LOAD HIGH AND TRAP (32H←32) (LFHAT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LOCFH, 0xff00000000ff0000, 0xeb00000000e00000, 0x0, // LOAD HIGH ON CONDITION (32) (LOCFH R1,D2(B2),M3)
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}},
+ {LOCFHR, 0xffff000000000000, 0xb9e0000000000000, 0xf0000000000, // LOAD HIGH ON CONDITION (32) (LOCFHR R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {LGFI, 0xff0f000000000000, 0xc001000000000000, 0x0, // LOAD IMMEDIATE (64→32) (LGFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {LXDB, 0xff00000000ff0000, 0xed00000000050000, 0xff000000, // LOAD LENGTHENED (long to extended BFP) (LXDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LXDBR, 0xffff000000000000, 0xb305000000000000, 0xff0000000000, // LOAD LENGTHENED (long to extended BFP) (LXDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LXDTR, 0xffff000000000000, 0xb3dc000000000000, 0xf00000000000, // LOAD LENGTHENED (long to extended DFP) (LXDTR R1,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_Mask_20_23}},
+ {LXD, 0xff00000000ff0000, 0xed00000000250000, 0xff000000, // LOAD LENGTHENED (long to extended HFP) (LXD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LXDR, 0xffff000000000000, 0xb325000000000000, 0xff0000000000, // LOAD LENGTHENED (long to extended HFP) (LXDR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LXEB, 0xff00000000ff0000, 0xed00000000060000, 0xff000000, // LOAD LENGTHENED (short to extended BFP) (LXEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LXEBR, 0xffff000000000000, 0xb306000000000000, 0xff0000000000, // LOAD LENGTHENED (short to extended BFP) (LXEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LXE, 0xff00000000ff0000, 0xed00000000260000, 0xff000000, // LOAD LENGTHENED (short to extended HFP) (LXE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LXER, 0xffff000000000000, 0xb326000000000000, 0xff0000000000, // LOAD LENGTHENED (short to extended HFP) (LXER R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LDEB, 0xff00000000ff0000, 0xed00000000040000, 0xff000000, // LOAD LENGTHENED (short to long BFP) (LDEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LDEBR, 0xffff000000000000, 0xb304000000000000, 0xff0000000000, // LOAD LENGTHENED (short to long BFP) (LDEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LDETR, 0xffff000000000000, 0xb3d4000000000000, 0xf00000000000, // LOAD LENGTHENED (short to long DFP) (LDETR R1,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_Mask_20_23}},
+ {LDE, 0xff00000000ff0000, 0xed00000000240000, 0xff000000, // LOAD LENGTHENED (short to long HFP) (LDE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LDER, 0xffff000000000000, 0xb324000000000000, 0xff0000000000, // LOAD LENGTHENED (short to long HFP) (LDER R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LLGF, 0xff00000000ff0000, 0xe300000000160000, 0x0, // LOAD LOGICAL (64←32) (LLGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLGFR, 0xffff000000000000, 0xb916000000000000, 0xff0000000000, // LOAD LOGICAL (64←32) (LLGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LLGFSG, 0xff00000000ff0000, 0xe300000000480000, 0x0, // LOAD LOGICAL AND SHIFT GUARDED (64←32) (LLGFSG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLGFAT, 0xff00000000ff0000, 0xe3000000009d0000, 0x0, // LOAD LOGICAL AND TRAP (64→32) (LLGFAT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLZRGF, 0xff00000000ff0000, 0xe3000000003a0000, 0x0, // LOAD LOGICAL AND ZERO RIGHTMOST BYTE(64→32) (LLZRGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLC, 0xff00000000ff0000, 0xe300000000940000, 0x0, // LOAD LOGICAL CHARACTER (32→8) (LLC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLCR, 0xffff000000000000, 0xb994000000000000, 0xff0000000000, // LOAD LOGICAL CHARACTER (32←8) (LLCR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LLGC, 0xff00000000ff0000, 0xe300000000900000, 0x0, // LOAD LOGICAL CHARACTER (64←8) (LLGC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLGCR, 0xffff000000000000, 0xb984000000000000, 0xff0000000000, // LOAD LOGICAL CHARACTER (64←8) (LLGCR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LLCH, 0xff00000000ff0000, 0xe300000000c20000, 0x0, // LOAD LOGICAL CHARACTER HIGH (32←8) (LLCH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLH, 0xff00000000ff0000, 0xe300000000950000, 0x0, // LOAD LOGICAL HALFWORD (32←16) (LLH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLHR, 0xffff000000000000, 0xb995000000000000, 0xff0000000000, // LOAD LOGICAL HALFWORD (32←16) (LLHR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LLGH, 0xff00000000ff0000, 0xe300000000910000, 0x0, // LOAD LOGICAL HALFWORD (64→16) (LLGH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLGHR, 0xffff000000000000, 0xb985000000000000, 0xff0000000000, // LOAD LOGICAL HALFWORD (64←16) (LLGHR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LLHH, 0xff00000000ff0000, 0xe300000000c60000, 0x0, // LOAD LOGICAL HALFWORD HIGH (32→16) (LLHH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLHRL, 0xff0f000000000000, 0xc402000000000000, 0x0, // LOAD LOGICAL HALFWORD RELATIVE LONG(32←16) (LLHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LLGHRL, 0xff0f000000000000, 0xc406000000000000, 0x0, // LOAD LOGICAL HALFWORD RELATIVE LONG(64→16) (LLGHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LLIHH, 0xff0f000000000000, 0xa50c000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high high) (LLIHH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {LLIHL, 0xff0f000000000000, 0xa50d000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high low) (LLIHL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {LLIHF, 0xff0f000000000000, 0xc00e000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high) (LLIHF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {LLILH, 0xff0f000000000000, 0xa50e000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low high) (LLILH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {LLILL, 0xff0f000000000000, 0xa50f000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low low) (LLILL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {LLILF, 0xff0f000000000000, 0xc00f000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low) (LLILF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {LLGFRL, 0xff0f000000000000, 0xc40e000000000000, 0x0, // LOAD LOGICAL RELATIVE LONG (64→32) (LLGFRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LLGT, 0xff00000000ff0000, 0xe300000000170000, 0x0, // LOAD LOGICAL THIRTY ONE BITS (64→31) (LLGT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LLGTR, 0xffff000000000000, 0xb917000000000000, 0xff0000000000, // LOAD LOGICAL THIRTY ONE BITS (64→31) (LLGTR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LLGTAT, 0xff00000000ff0000, 0xe3000000009c0000, 0x0, // LOAD LOGICAL THIRTY ONE BITS AND TRAP(64←31) (LLGTAT R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LM, 0xff00000000000000, 0x9800000000000000, 0x0, // LOAD MULTIPLE (32) (LM R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LMY, 0xff00000000ff0000, 0xeb00000000980000, 0x0, // LOAD MULTIPLE (32) (LMY R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LMG, 0xff00000000ff0000, 0xeb00000000040000, 0x0, // LOAD MULTIPLE (64) (LMG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LMD, 0xff00000000000000, 0xef00000000000000, 0x0, // LOAD MULTIPLE DISJOINT (64→32&32) (LMD R1,R3,D2(B2),D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {LMH, 0xff00000000ff0000, 0xeb00000000960000, 0x0, // LOAD MULTIPLE HIGH (32) (LMH R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LNR, 0xff00000000000000, 0x1100000000000000, 0x0, // LOAD NEGATIVE (32) (LNR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {LNGR, 0xffff000000000000, 0xb901000000000000, 0xff0000000000, // LOAD NEGATIVE (64) (LNGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LNGFR, 0xffff000000000000, 0xb911000000000000, 0xff0000000000, // LOAD NEGATIVE (64→32) (LNGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LNXBR, 0xffff000000000000, 0xb341000000000000, 0xff0000000000, // LOAD NEGATIVE (extended BFP) (LNXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LNXR, 0xffff000000000000, 0xb361000000000000, 0xff0000000000, // LOAD NEGATIVE (extended HFP) (LNXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LNDBR, 0xffff000000000000, 0xb311000000000000, 0xff0000000000, // LOAD NEGATIVE (long BFP) (LNDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LNDR, 0xff00000000000000, 0x2100000000000000, 0x0, // LOAD NEGATIVE (long HFP) (LNDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LNDFR, 0xffff000000000000, 0xb371000000000000, 0xff0000000000, // LOAD NEGATIVE (long) (LNDFR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LNEBR, 0xffff000000000000, 0xb301000000000000, 0xff0000000000, // LOAD NEGATIVE (short BFP) (LNEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LNER, 0xff00000000000000, 0x3100000000000000, 0x0, // LOAD NEGATIVE (short HFP) (LNER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LOC, 0xff00000000ff0000, 0xeb00000000f20000, 0x0, // LOAD ON CONDITION (32) (LOC R1,D2(B2),M3)
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}},
+ {LOCR, 0xffff000000000000, 0xb9f2000000000000, 0xf0000000000, // LOAD ON CONDITION (32) (LOCR R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {LOCG, 0xff00000000ff0000, 0xeb00000000e20000, 0x0, // LOAD ON CONDITION (64) (LOCG R1,D2(B2),M3)
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}},
+ {LOCGR, 0xffff000000000000, 0xb9e2000000000000, 0xf0000000000, // LOAD ON CONDITION (64) (LOCGR R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {LPTEA, 0xffff000000000000, 0xb9aa000000000000, 0x0, // LOAD PAGE TABLE ENTRY ADDRESS (LPTEA R1,R3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {LPD, 0xff0f000000000000, 0xc804000000000000, 0x0, // LOAD PAIR DISJOINT (32) (LPD R3,D1(B1),D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {LPDG, 0xff0f000000000000, 0xc805000000000000, 0x0, // LOAD PAIR DISJOINT (64) (LPDG R3,D1(B1),D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {LPQ, 0xff00000000ff0000, 0xe3000000008f0000, 0x0, // LOAD PAIR FROM QUADWORD (64&64←128) (LPQ R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LPR, 0xff00000000000000, 0x1000000000000000, 0x0, // LOAD POSITIVE (32) (LPR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {LPGR, 0xffff000000000000, 0xb900000000000000, 0xff0000000000, // LOAD POSITIVE (64) (LPGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LPGFR, 0xffff000000000000, 0xb910000000000000, 0xff0000000000, // LOAD POSITIVE (64→32) (LPGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LPXBR, 0xffff000000000000, 0xb340000000000000, 0xff0000000000, // LOAD POSITIVE (extended BFP) (LPXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LPXR, 0xffff000000000000, 0xb360000000000000, 0xff0000000000, // LOAD POSITIVE (extended HFP) (LPXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LPDBR, 0xffff000000000000, 0xb310000000000000, 0xff0000000000, // LOAD POSITIVE (long BFP) (LPDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LPDR, 0xff00000000000000, 0x2000000000000000, 0x0, // LOAD POSITIVE (long HFP) (LPDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LPDFR, 0xffff000000000000, 0xb370000000000000, 0xff0000000000, // LOAD POSITIVE (long) (LPDFR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LPEBR, 0xffff000000000000, 0xb300000000000000, 0xff0000000000, // LOAD POSITIVE (short BFP) (LPEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LPER, 0xff00000000000000, 0x3000000000000000, 0x0, // LOAD POSITIVE (short HFP) (LPER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LPSW, 0xff00000000000000, 0x8200000000000000, 0x0, // LOAD PSW (LPSW D1(B1))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LPSWE, 0xffff000000000000, 0xb2b2000000000000, 0x0, // LOAD PSW EXTENDED (LPSWE D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {LPSWEY, 0xff00000000ff0000, 0xeb00000000710000, 0xff000000000000, // LOAD PSW EXTENDED (LPSWEY D1(B1))
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {LRA, 0xff00000000000000, 0xb100000000000000, 0x0, // LOAD REAL ADDRESS (32) (LRA R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LRAY, 0xff00000000ff0000, 0xe300000000130000, 0x0, // LOAD REAL ADDRESS (32) (LRAY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LRAG, 0xff00000000ff0000, 0xe300000000030000, 0x0, // LOAD REAL ADDRESS (64) (LRAG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LRL, 0xff0f000000000000, 0xc40d000000000000, 0x0, // LOAD RELATIVE LONG (32) (LRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LGRL, 0xff0f000000000000, 0xc408000000000000, 0x0, // LOAD RELATIVE LONG (64) (LGRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LGFRL, 0xff0f000000000000, 0xc40c000000000000, 0x0, // LOAD RELATIVE LONG (64→32) (LGFRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {LRVH, 0xff00000000ff0000, 0xe3000000001f0000, 0x0, // LOAD REVERSED (16) (LRVH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LRV, 0xff00000000ff0000, 0xe3000000001e0000, 0x0, // LOAD REVERSED (32) (LRV R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LRVR, 0xffff000000000000, 0xb91f000000000000, 0xff0000000000, // LOAD REVERSED (32) (LRVR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LRVG, 0xff00000000ff0000, 0xe3000000000f0000, 0x0, // LOAD REVERSED (64) (LRVG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {LRVGR, 0xffff000000000000, 0xb90f000000000000, 0xff0000000000, // LOAD REVERSED (64) (LRVGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LDXBR, 0xffff000000000000, 0xb345000000000000, 0xff0000000000, // LOAD ROUNDED (extended to long BFP) (LDXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LDXBRA, 0xffff000000000000, 0xb345000000000000, 0x0, // LOAD ROUNDED (extended to long BFP) (LDXBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {LDXTR, 0xffff000000000000, 0xb3dd000000000000, 0x0, // LOAD ROUNDED (extended to long DFP) (LDXTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {LDXR, 0xff00000000000000, 0x2500000000000000, 0x0, // LOAD ROUNDED (extended to long HFP) (LDXR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LRDR, 0xff00000000000000, 0x2500000000000000, 0x0, // LOAD ROUNDED (extended to long HFP) (LRDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LEXBR, 0xffff000000000000, 0xb346000000000000, 0xff0000000000, // LOAD ROUNDED (extended to short BFP) (LEXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LEXBRA, 0xffff000000000000, 0xb346000000000000, 0x0, // LOAD ROUNDED (extended to short BFP) (LEXBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {LEXR, 0xffff000000000000, 0xb366000000000000, 0xff0000000000, // LOAD ROUNDED (extended to short HFP) (LEXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LEDBR, 0xffff000000000000, 0xb344000000000000, 0xff0000000000, // LOAD ROUNDED (long to short BFP) (LEDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {LEDBRA, 0xffff000000000000, 0xb344000000000000, 0x0, // LOAD ROUNDED (long to short BFP) (LEDBRA R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {LEDTR, 0xffff000000000000, 0xb3d5000000000000, 0x0, // LOAD ROUNDED (long to short DFP) (LEDTR R1,M3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {LEDR, 0xff00000000000000, 0x3500000000000000, 0x0, // LOAD ROUNDED (long to short HFP) (LEDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LRER, 0xff00000000000000, 0x3500000000000000, 0x0, // LOAD ROUNDED (long to short HFP) (LRER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {LURA, 0xffff000000000000, 0xb24b000000000000, 0xff0000000000, // LOAD USING REAL ADDRESS (32) (LURA R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LURAG, 0xffff000000000000, 0xb905000000000000, 0xff0000000000, // LOAD USING REAL ADDRESS (64) (LURAG R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {LZXR, 0xffff000000000000, 0xb376000000000000, 0xff0f00000000, // LOAD ZERO (extended) (LZXR R1)
+ [8]*argField{ap_FPReg_24_27}},
+ {LZDR, 0xffff000000000000, 0xb375000000000000, 0xff0f00000000, // LOAD ZERO (long) (LZDR R1)
+ [8]*argField{ap_FPReg_24_27}},
+ {LZER, 0xffff000000000000, 0xb374000000000000, 0xff0f00000000, // LOAD ZERO (short) (LZER R1)
+ [8]*argField{ap_FPReg_24_27}},
+ {MSTA, 0xffff000000000000, 0xb247000000000000, 0xff0f00000000, // MODIFY STACKED STATE (MSTA R1)
+ [8]*argField{ap_Reg_24_27}},
+ {MSCH, 0xffff000000000000, 0xb232000000000000, 0x0, // MODIFY SUBCHANNEL (MSCH D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {MC, 0xff00000000000000, 0xaf00000000000000, 0x0, // MONITOR CALL (MC D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {MVHHI, 0xffff000000000000, 0xe544000000000000, 0x0, // MOVE (16←16) (MVHHI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}},
+ {MVHI, 0xffff000000000000, 0xe54c000000000000, 0x0, // MOVE (32→16) (MVHI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}},
+ {MVGHI, 0xffff000000000000, 0xe548000000000000, 0x0, // MOVE (64←16) (MVGHI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}},
+ {MVC, 0xff00000000000000, 0xd200000000000000, 0x0, // MOVE (character) (MVC D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {MVI, 0xff00000000000000, 0x9200000000000000, 0x0, // MOVE (immediate) (MVI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {MVIY, 0xff00000000ff0000, 0xeb00000000520000, 0x0, // MOVE (immediate) (MVIY D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {MVCIN, 0xff00000000000000, 0xe800000000000000, 0x0, // MOVE INVERSE (MVCIN D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {MVCL, 0xff00000000000000, 0xe00000000000000, 0x0, // MOVE LONG (MVCL R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {MVCLE, 0xff00000000000000, 0xa800000000000000, 0x0, // MOVE LONG EXTENDED (MVCLE R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {MVCLU, 0xff00000000ff0000, 0xeb000000008e0000, 0x0, // MOVE LONG UNICODE (MVCLU R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {MVN, 0xff00000000000000, 0xd100000000000000, 0x0, // MOVE NUMERICS (MVN D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {MVPG, 0xffff000000000000, 0xb254000000000000, 0xff0000000000, // MOVE PAGE (MVPG R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {MVCRL, 0xffff000000000000, 0xe50a000000000000, 0x0, // MOVE RIGHT TO LEFT (MVCRL D1(B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {MVST, 0xffff000000000000, 0xb255000000000000, 0xff0000000000, // MOVE STRING (MVST R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {MVCP, 0xff00000000000000, 0xda00000000000000, 0x0, // MOVE TO PRIMARY (MVCP D1(R1,B1),D2(B2),R3)
+ [8]*argField{ap_DispUnsigned_20_31, ap_Reg_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_12_15}},
+ {MVCS, 0xff00000000000000, 0xdb00000000000000, 0x0, // MOVE TO SECONDARY (MVCS D1(R1,B1),D2(B2),R3)
+ [8]*argField{ap_DispUnsigned_20_31, ap_Reg_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_12_15}},
+ {MVCDK, 0xffff000000000000, 0xe50f000000000000, 0x0, // MOVE WITH DESTINATION KEY (MVCDK D1(B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {MVCK, 0xff00000000000000, 0xd900000000000000, 0x0, // MOVE WITH KEY (MVCK D1(R1,B1),D2(B2),R3)
+ [8]*argField{ap_DispUnsigned_20_31, ap_Reg_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_12_15}},
+ {MVO, 0xff00000000000000, 0xf100000000000000, 0x0, // MOVE WITH OFFSET (MVO D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {MVCOS, 0xff0f000000000000, 0xc800000000000000, 0x0, // MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS D1(B1),D2(B2),R3)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_8_11}},
+ {MVCSK, 0xffff000000000000, 0xe50e000000000000, 0x0, // MOVE WITH SOURCE KEY (MVCSK D1(B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {MVZ, 0xff00000000000000, 0xd300000000000000, 0x0, // MOVE ZONES (MVZ D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {MG, 0xff00000000ff0000, 0xe300000000840000, 0x0, // MULTIPLY (128←64) (MG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MGRK, 0xffff000000000000, 0xb9ec000000000000, 0xf0000000000, // MULTIPLY (128←64) (MGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {M, 0xff00000000000000, 0x5c00000000000000, 0x0, // MULTIPLY (64←32) (M R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MFY, 0xff00000000ff0000, 0xe3000000005c0000, 0x0, // MULTIPLY (64←32) (MFY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MR, 0xff00000000000000, 0x1c00000000000000, 0x0, // MULTIPLY (64←32) (MR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {MXBR, 0xffff000000000000, 0xb34c000000000000, 0xff0000000000, // MULTIPLY (extended BFP) (MXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MXTR, 0xffff000000000000, 0xb3d8000000000000, 0xf0000000000, // MULTIPLY (extended DFP) (MXTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {MXTRA, 0xffff000000000000, 0xb3d8000000000000, 0x0, // MULTIPLY (extended DFP) (MXTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {MXR, 0xff00000000000000, 0x2600000000000000, 0x0, // MULTIPLY (extended HFP) (MXR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {MDB, 0xff00000000ff0000, 0xed000000001c0000, 0xff000000, // MULTIPLY (long BFP) (MDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MDBR, 0xffff000000000000, 0xb31c000000000000, 0xff0000000000, // MULTIPLY (long BFP) (MDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MDTR, 0xffff000000000000, 0xb3d0000000000000, 0xf0000000000, // MULTIPLY (long DFP) (MDTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {MDTRA, 0xffff000000000000, 0xb3d0000000000000, 0x0, // MULTIPLY (long DFP) (MDTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {MD, 0xff00000000000000, 0x6c00000000000000, 0x0, // MULTIPLY (long HFP) (MD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MDR, 0xff00000000000000, 0x2c00000000000000, 0x0, // MULTIPLY (long HFP) (MDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {MXDB, 0xff00000000ff0000, 0xed00000000070000, 0xff000000, // MULTIPLY (long to extended BFP) (MXDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MXDBR, 0xffff000000000000, 0xb307000000000000, 0xff0000000000, // MULTIPLY (long to extended BFP) (MXDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MXD, 0xff00000000000000, 0x6700000000000000, 0x0, // MULTIPLY (long to extended HFP) (MXD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MXDR, 0xff00000000000000, 0x2700000000000000, 0x0, // MULTIPLY (long to extended HFP) (MXDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {MEEB, 0xff00000000ff0000, 0xed00000000170000, 0xff000000, // MULTIPLY (short BFP) (MEEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MEEBR, 0xffff000000000000, 0xb317000000000000, 0xff0000000000, // MULTIPLY (short BFP) (MEEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MEE, 0xff00000000ff0000, 0xed00000000370000, 0xff000000, // MULTIPLY (short HFP) (MEE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MEER, 0xffff000000000000, 0xb337000000000000, 0xff0000000000, // MULTIPLY (short HFP) (MEER R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MDEB, 0xff00000000ff0000, 0xed000000000c0000, 0xff000000, // MULTIPLY (short to long BFP) (MDEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MDEBR, 0xffff000000000000, 0xb30c000000000000, 0xff0000000000, // MULTIPLY (short to long BFP) (MDEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MDE, 0xff00000000000000, 0x7c00000000000000, 0x0, // MULTIPLY (short to long HFP) (MDE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MDER, 0xff00000000000000, 0x3c00000000000000, 0x0, // MULTIPLY (short to long HFP) (MDER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {ME, 0xff00000000000000, 0x7c00000000000000, 0x0, // MULTIPLY (short to long HFP) (ME R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MER, 0xff00000000000000, 0x3c00000000000000, 0x0, // MULTIPLY (short to long HFP) (MER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {MAY, 0xff00000000ff0000, 0xed000000003a0000, 0xf000000, // MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) (MAY R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MAYR, 0xffff000000000000, 0xb33a000000000000, 0xf0000000000, // MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) (MAYR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MADB, 0xff00000000ff0000, 0xed000000001e0000, 0xf000000, // MULTIPLY AND ADD (long BFP) (MADB R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MADBR, 0xffff000000000000, 0xb31e000000000000, 0xf0000000000, // MULTIPLY AND ADD (long BFP) (MADBR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MAD, 0xff00000000ff0000, 0xed000000003e0000, 0xf000000, // MULTIPLY AND ADD (long HFP) (MAD R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MADR, 0xffff000000000000, 0xb33e000000000000, 0xf0000000000, // MULTIPLY AND ADD (long HFP) (MADR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MAEB, 0xff00000000ff0000, 0xed000000000e0000, 0xf000000, // MULTIPLY AND ADD (short BFP) (MAEB R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MAEBR, 0xffff000000000000, 0xb30e000000000000, 0xf0000000000, // MULTIPLY AND ADD (short BFP) (MAEBR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MAE, 0xff00000000ff0000, 0xed000000002e0000, 0xf000000, // MULTIPLY AND ADD (short HFP) (MAE R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MAER, 0xffff000000000000, 0xb32e000000000000, 0xf0000000000, // MULTIPLY AND ADD (short HFP) (MAER R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MAYH, 0xff00000000ff0000, 0xed000000003c0000, 0xf000000, // MULTIPLY AND ADD UNNRM. (long to ext. high HFP) (MAYH R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MAYHR, 0xffff000000000000, 0xb33c000000000000, 0xf0000000000, // MULTIPLY AND ADD UNNRM. (long to ext. high HFP) (MAYHR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MAYL, 0xff00000000ff0000, 0xed00000000380000, 0xf000000, // MULTIPLY AND ADD UNNRM. (long to ext. low HFP) (MAYL R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MAYLR, 0xffff000000000000, 0xb338000000000000, 0xf0000000000, // MULTIPLY AND ADD UNNRM. (long to ext. low HFP) (MAYLR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MSDB, 0xff00000000ff0000, 0xed000000001f0000, 0xf000000, // MULTIPLY AND SUBTRACT (long BFP) (MSDB R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSDBR, 0xffff000000000000, 0xb31f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (long BFP) (MSDBR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MSD, 0xff00000000ff0000, 0xed000000003f0000, 0xf000000, // MULTIPLY AND SUBTRACT (long HFP) (MSD R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSDR, 0xffff000000000000, 0xb33f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (long HFP) (MSDR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MSEB, 0xff00000000ff0000, 0xed000000000f0000, 0xf000000, // MULTIPLY AND SUBTRACT (short BFP) (MSEB R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSEBR, 0xffff000000000000, 0xb30f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (short BFP) (MSEBR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MSE, 0xff00000000ff0000, 0xed000000002f0000, 0xf000000, // MULTIPLY AND SUBTRACT (short HFP) (MSE R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSER, 0xffff000000000000, 0xb32f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (short HFP) (MSER R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MP, 0xff00000000000000, 0xfc00000000000000, 0x0, // MULTIPLY DECIMAL (MP D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {MH, 0xff00000000000000, 0x4c00000000000000, 0x0, // MULTIPLY HALFWORD (32←16) (MH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MHY, 0xff00000000ff0000, 0xe3000000007c0000, 0x0, // MULTIPLY HALFWORD (32←16) (MHY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MGH, 0xff00000000ff0000, 0xe3000000003c0000, 0x0, // MULTIPLY HALFWORD (64→16) (MGH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MHI, 0xff0f000000000000, 0xa70c000000000000, 0x0, // MULTIPLY HALFWORD IMMEDIATE (32→16) (MHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {MGHI, 0xff0f000000000000, 0xa70d000000000000, 0x0, // MULTIPLY HALFWORD IMMEDIATE (64→16) (MGHI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {MLG, 0xff00000000ff0000, 0xe300000000860000, 0x0, // MULTIPLY LOGICAL (128→64) (MLG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MLGR, 0xffff000000000000, 0xb986000000000000, 0xff0000000000, // MULTIPLY LOGICAL (128→64) (MLGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {ML, 0xff00000000ff0000, 0xe300000000960000, 0x0, // MULTIPLY LOGICAL (64←32) (ML R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MLR, 0xffff000000000000, 0xb996000000000000, 0xff0000000000, // MULTIPLY LOGICAL (64←32) (MLR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {MS, 0xff00000000000000, 0x7100000000000000, 0x0, // MULTIPLY SINGLE (32) (MS R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSC, 0xff00000000ff0000, 0xe300000000530000, 0x0, // MULTIPLY SINGLE (32) (MSC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSR, 0xffff000000000000, 0xb252000000000000, 0xff0000000000, // MULTIPLY SINGLE (32) (MSR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {MSRKC, 0xffff000000000000, 0xb9fd000000000000, 0xf0000000000, // MULTIPLY SINGLE (32) (MSRKC R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {MSY, 0xff00000000ff0000, 0xe300000000510000, 0x0, // MULTIPLY SINGLE (32) (MSY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSG, 0xff00000000ff0000, 0xe3000000000c0000, 0x0, // MULTIPLY SINGLE (64) (MSG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSGC, 0xff00000000ff0000, 0xe300000000830000, 0x0, // MULTIPLY SINGLE (64) (MSGC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSGR, 0xffff000000000000, 0xb90c000000000000, 0xff0000000000, // MULTIPLY SINGLE (64) (MSGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {MSGRKC, 0xffff000000000000, 0xb9ed000000000000, 0xf0000000000, // MULTIPLY SINGLE (64) (MSGRKC R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {MSGF, 0xff00000000ff0000, 0xe3000000001c0000, 0x0, // MULTIPLY SINGLE (64←32) (MSGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MSGFR, 0xffff000000000000, 0xb91c000000000000, 0xff0000000000, // MULTIPLY SINGLE (64←32) (MSGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {MSFI, 0xff0f000000000000, 0xc201000000000000, 0x0, // MULTIPLY SINGLE IMMEDIATE (32) (MSFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {MSGFI, 0xff0f000000000000, 0xc200000000000000, 0x0, // MULTIPLY SINGLE IMMEDIATE (64←32) (MSGFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {MYH, 0xff00000000ff0000, 0xed000000003d0000, 0xf000000, // MULTIPLY UNNORM. (long to ext. high HFP) (MYH R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MYHR, 0xffff000000000000, 0xb33d000000000000, 0xf0000000000, // MULTIPLY UNNORM. (long to ext. high HFP) (MYHR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MYL, 0xff00000000ff0000, 0xed00000000390000, 0xf000000, // MULTIPLY UNNORM. (long to ext. low HFP) (MYL R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MYLR, 0xffff000000000000, 0xb339000000000000, 0xf0000000000, // MULTIPLY UNNORM. (long to ext. low HFP) (MYLR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {MY, 0xff00000000ff0000, 0xed000000003b0000, 0xf000000, // MULTIPLY UNNORMALIZED (long to ext. HFP) (MY R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {MYR, 0xffff000000000000, 0xb33b000000000000, 0xf0000000000, // MULTIPLY UNNORMALIZED (long to ext. HFP) (MYR R1,R3,R2)
+ [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}},
+ {NNRK, 0xffff000000000000, 0xb974000000000000, 0xf0000000000, // NAND (32) (NNRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NNGRK, 0xffff000000000000, 0xb964000000000000, 0xf0000000000, // NAND (64) (NNGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NNPA, 0xffff000000000000, 0xb93b000000000000, 0xffff00000000, // NEURAL NETWORK PROCESSING ASSIST (NNPA)
+ [8]*argField{}},
+ {NIAI, 0xffff000000000000, 0xb2fa000000000000, 0xff0000000000, // NEXT INSTRUCTION ACCESS INTENT (NIAI I1,I2)
+ [8]*argField{ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
+ {NTSTG, 0xff00000000ff0000, 0xe300000000250000, 0x0, // NONTRANSACTIONAL STORE (64) (NTSTG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {NORK, 0xffff000000000000, 0xb976000000000000, 0xf0000000000, // NOR (32) (NORK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NOGRK, 0xffff000000000000, 0xb966000000000000, 0xf0000000000, // NOR (64) (NOGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NXRK, 0xffff000000000000, 0xb977000000000000, 0xf0000000000, // NOT EXCLUSIVE OR (32) (NXRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {NXGRK, 0xffff000000000000, 0xb967000000000000, 0xf0000000000, // NOT EXCLUSIVE OR (64) (NXGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {O, 0xff00000000000000, 0x5600000000000000, 0x0, // OR (32) (O R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {OR, 0xff00000000000000, 0x1600000000000000, 0x0, // OR (32) (OR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {ORK, 0xffff000000000000, 0xb9f6000000000000, 0xf0000000000, // OR (32) (ORK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {OY, 0xff00000000ff0000, 0xe300000000560000, 0x0, // OR (32) (OY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {OG, 0xff00000000ff0000, 0xe300000000810000, 0x0, // OR (64) (OG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {OGR, 0xffff000000000000, 0xb981000000000000, 0xff0000000000, // OR (64) (OGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {OGRK, 0xffff000000000000, 0xb9e6000000000000, 0xf0000000000, // OR (64) (OGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {OC, 0xff00000000000000, 0xd600000000000000, 0x0, // OR (character) (OC D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {OI, 0xff00000000000000, 0x9600000000000000, 0x0, // OR (immediate) (OI D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {OIY, 0xff00000000ff0000, 0xeb00000000560000, 0x0, // OR (immediate) (OIY D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {OIHH, 0xff0f000000000000, 0xa508000000000000, 0x0, // OR IMMEDIATE (high high) (OIHH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {OIHL, 0xff0f000000000000, 0xa509000000000000, 0x0, // OR IMMEDIATE (high low) (OIHL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {OIHF, 0xff0f000000000000, 0xc00c000000000000, 0x0, // OR IMMEDIATE (high) (OIHF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {OILH, 0xff0f000000000000, 0xa50a000000000000, 0x0, // OR IMMEDIATE (low high) (OILH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {OILL, 0xff0f000000000000, 0xa50b000000000000, 0x0, // OR IMMEDIATE (low low) (OILL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {OILF, 0xff0f000000000000, 0xc00d000000000000, 0x0, // OR IMMEDIATE (low) (OILF R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {OCRK, 0xffff000000000000, 0xb975000000000000, 0xf0000000000, // OR WITH COMPLEMENT (32) (OCRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {OCGRK, 0xffff000000000000, 0xb965000000000000, 0xf0000000000, // OR WITH COMPLEMENT (64) (OCGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {PACK, 0xff00000000000000, 0xf200000000000000, 0x0, // PACK (PACK D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {PKA, 0xff00000000000000, 0xe900000000000000, 0x0, // PACK ASCII (PKA D1(B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_8_15, ap_BaseReg_32_35}},
+ {PKU, 0xff00000000000000, 0xe100000000000000, 0x0, // PACK UNICODE (PKU D1(B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_8_15, ap_BaseReg_32_35}},
+ {PGIN, 0xffff000000000000, 0xb22e000000000000, 0xff0000000000, // PAGE IN (PGIN R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {PGOUT, 0xffff000000000000, 0xb22f000000000000, 0xff0000000000, // PAGE OUT (PGOUT R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {PCC, 0xffff000000000000, 0xb92c000000000000, 0xffff00000000, // PERFORM CRYPTOGRAPHIC COMPUTATION (PCC)
+ [8]*argField{}},
+ {PCKMO, 0xffff000000000000, 0xb928000000000000, 0xffff00000000, // PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS (PCKMO)
+ [8]*argField{}},
+ {PFPO, 0xffff000000000000, 0x10a000000000000, 0x0, // PERFORM FLOATING-POINT OPERATION (PFPO)
+ [8]*argField{}},
+ {PFMF, 0xffff000000000000, 0xb9af000000000000, 0xff0000000000, // PERFORM FRAME MANAGEMENT FUNCTION (PFMF R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {PLO, 0xff00000000000000, 0xee00000000000000, 0x0, // PERFORM LOCKED OPERATION (PLO R1,D2(B2),R3,D4(B4))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Reg_12_15, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {PPA, 0xffff000000000000, 0xb2e8000000000000, 0xf0000000000, // PERFORM PROCESSOR ASSIST (PPA R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {PRNO, 0xffff000000000000, 0xb93c000000000000, 0xff0000000000, // PERFORM RANDOM NUMBER OPERATION (PRNO R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {PTFF, 0xffff000000000000, 0x104000000000000, 0x0, // PERFORM TIMING FACILITY FUNCTION (PTFF)
+ [8]*argField{}},
+ {PTF, 0xffff000000000000, 0xb9a2000000000000, 0xff0f00000000, // PERFORM TOPOLOGY FUNCTION (PTF R1)
+ [8]*argField{ap_Reg_24_27}},
+ {POPCNT, 0xffff000000000000, 0xb9e1000000000000, 0xf0000000000, // POPULATION COUNT (POPCNT R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {PFD, 0xff00000000ff0000, 0xe300000000360000, 0x0, // PREFETCH DATA (PFD M1,D2(X2,B2))
+ [8]*argField{ap_Mask_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {PFDRL, 0xff0f000000000000, 0xc602000000000000, 0x0, // PREFETCH DATA RELATIVE LONG (PFDRL M1,RI2)
+ [8]*argField{ap_Mask_8_11, ap_RegImSigned32_16_47}},
+ {PC, 0xffff000000000000, 0xb218000000000000, 0x0, // PROGRAM CALL (PC D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {PR, 0xffff000000000000, 0x101000000000000, 0x0, // PROGRAM RETURN (PR)
+ [8]*argField{}},
+ {PT, 0xffff000000000000, 0xb228000000000000, 0xff0000000000, // PROGRAM TRANSFER (PT R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {PTI, 0xffff000000000000, 0xb99e000000000000, 0xff0000000000, // PROGRAM TRANSFER WITH INSTANCE (PTI R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {PALB, 0xffff000000000000, 0xb248000000000000, 0xffff00000000, // PURGE ALB (PALB)
+ [8]*argField{}},
+ {PTLB, 0xffff000000000000, 0xb20d000000000000, 0xffff00000000, // PURGE TLB (PTLB)
+ [8]*argField{}},
+ {QAXTR, 0xffff000000000000, 0xb3fd000000000000, 0x0, // QUANTIZE (extended DFP) (QAXTR R1,R3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {QADTR, 0xffff000000000000, 0xb3f5000000000000, 0x0, // QUANTIZE (long DFP) (QADTR R1,R3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}},
+ {QPACI, 0xffff000000000000, 0xb28f000000000000, 0x0, // QUERY PROCESSOR ACTIVITY COUNTER INFORMATION (QPACI D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {RRXTR, 0xffff000000000000, 0xb3ff000000000000, 0x0, // REROUND (extended DFP) (RRXTR R1,R3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {RRDTR, 0xffff000000000000, 0xb3f7000000000000, 0x0, // REROUND (long DFP) (RRDTR R1,R3,R2,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {RCHP, 0xffff000000000000, 0xb23b000000000000, 0xffff00000000, // RESET CHANNEL PATH (RCHP)
+ [8]*argField{}},
+ {RDP, 0xffff000000000000, 0xb98b000000000000, 0x0, // RESET DAT PROTECTION (RDP R1,R3,R2,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}},
+ {RRBE, 0xffff000000000000, 0xb22a000000000000, 0xff0000000000, // RESET REFERENCE BIT EXTENDED (RRBE R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {RRBM, 0xffff000000000000, 0xb9ae000000000000, 0xff0000000000, // RESET REFERENCE BITS MULTIPLE (RRBM R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {RP, 0xffff000000000000, 0xb277000000000000, 0x0, // RESUME PROGRAM (RP D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {RSCH, 0xffff000000000000, 0xb238000000000000, 0xffff00000000, // RESUME SUBCHANNEL (RSCH)
+ [8]*argField{}},
+ {RLL, 0xff00000000ff0000, 0xeb000000001d0000, 0x0, // ROTATE LEFT SINGLE LOGICAL (32) (RLL R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {RLLG, 0xff00000000ff0000, 0xeb000000001c0000, 0x0, // ROTATE LEFT SINGLE LOGICAL (64) (RLLG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {RNSBG, 0xff00000000ff0000, 0xec00000000540000, 0x0, // ROTATE THEN AND SELECTED BITS (64) (RNSBG R1,R2,I3,I4,I5)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}},
+ {RXSBG, 0xff00000000ff0000, 0xec00000000570000, 0x0, // ROTATETHENEXCLUSIVEORSELECT.BITS(64) (RXSBG R1,R2,I3,I4,I5)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}},
+ {RISBG, 0xff00000000ff0000, 0xec00000000550000, 0x0, // ROTATE THEN INSERT SELECTED BITS (64) (RISBG R1,R2,I3,I4,I5)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}},
+ {RISBGN, 0xff00000000ff0000, 0xec00000000590000, 0x0, // ROTATE THEN INSERT SELECTED BITS (64) (RISBGN R1,R2,I3,I4,I5)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}},
+ {RISBHG, 0xff00000000ff0000, 0xec000000005d0000, 0x0, // ROTATE THEN INSERT SELECTED BITS HIGH(64) (RISBHG R1,R2,I3,I4,I5)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}},
+ {RISBLG, 0xff00000000ff0000, 0xec00000000510000, 0x0, // ROTATE THEN INSERT SELECTED BITS LOW (64) (RISBLG R1,R2,I3,I4,I5)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}},
+ {ROSBG, 0xff00000000ff0000, 0xec00000000560000, 0x0, // ROTATE THEN OR SELECTED BITS (64) (ROSBG R1,R2,I3,I4,I5)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}},
+ {SRST, 0xffff000000000000, 0xb25e000000000000, 0xff0000000000, // SEARCH STRING (SRST R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SRSTU, 0xffff000000000000, 0xb9be000000000000, 0xff0000000000, // SEARCH STRING UNICODE (SRSTU R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SELR, 0xffff000000000000, 0xb9f0000000000000, 0x0, // SELECT (32) (SELR R1,R2,R3,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}},
+ {SELGR, 0xffff000000000000, 0xb9e3000000000000, 0x0, // SELECT (64) (SELGR R1,R2,R3,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}},
+ {SELFHR, 0xffff000000000000, 0xb9c0000000000000, 0x0, // SELECT HIGH (32) (SELFHR R1,R2,R3,M4)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}},
+ {SAR, 0xffff000000000000, 0xb24e000000000000, 0xff0000000000, // SET ACCESS (SAR R1,R2)
+ [8]*argField{ap_ACReg_24_27, ap_Reg_28_31}},
+ {SAL, 0xffff000000000000, 0xb237000000000000, 0xffff00000000, // SET ADDRESS LIMIT (SAL)
+ [8]*argField{}},
+ {SAC, 0xffff000000000000, 0xb219000000000000, 0x0, // SET ADDRESS SPACE CONTROL (SAC D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SACF, 0xffff000000000000, 0xb279000000000000, 0x0, // SET ADDRESS SPACE CONTROL FAST (SACF D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SAM24, 0xffff000000000000, 0x10c000000000000, 0x0, // SET ADDRESSING MODE (24) (SAM24)
+ [8]*argField{}},
+ {SAM31, 0xffff000000000000, 0x10d000000000000, 0x0, // SET ADDRESSING MODE (31) (SAM31)
+ [8]*argField{}},
+ {SAM64, 0xffff000000000000, 0x10e000000000000, 0x0, // SET ADDRESSING MODE (64) (SAM64)
+ [8]*argField{}},
+ {SRNM, 0xffff000000000000, 0xb299000000000000, 0x0, // SET BFP ROUNDING MODE (2 bit) (SRNM D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SRNMB, 0xffff000000000000, 0xb2b8000000000000, 0x0, // SET BFP ROUNDING MODE (3 bit) (SRNMB D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SCHM, 0xffff000000000000, 0xb23c000000000000, 0xffff00000000, // SET CHANNEL MONITOR (SCHM)
+ [8]*argField{}},
+ {SCK, 0xffff000000000000, 0xb204000000000000, 0x0, // SET CLOCK (SCK D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SCKC, 0xffff000000000000, 0xb206000000000000, 0x0, // SET CLOCK COMPARATOR (SCKC D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SCKPF, 0xffff000000000000, 0x107000000000000, 0x0, // SET CLOCK PROGRAMMABLE FIELD (SCKPF)
+ [8]*argField{}},
+ {SPT, 0xffff000000000000, 0xb208000000000000, 0x0, // SET CPU TIMER (SPT D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SRNMT, 0xffff000000000000, 0xb2b9000000000000, 0x0, // SET DFP ROUNDING MODE (SRNMT D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SFPC, 0xffff000000000000, 0xb384000000000000, 0xff0f00000000, // SET FPC (SFPC R1)
+ [8]*argField{ap_Reg_24_27}},
+ {SFASR, 0xffff000000000000, 0xb385000000000000, 0xff0f00000000, // SET FPC AND SIGNAL (SFASR R1)
+ [8]*argField{ap_Reg_24_27}},
+ {SPX, 0xffff000000000000, 0xb210000000000000, 0x0, // SET PREFIX (SPX D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SPM, 0xff00000000000000, 0x400000000000000, 0xf000000000000, // SET PROGRAM MASK (SPM R1)
+ [8]*argField{ap_Reg_8_11}},
+ {SPKA, 0xffff000000000000, 0xb20a000000000000, 0x0, // SET PSW KEY FROM ADDRESS (SPKA D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SSAR, 0xffff000000000000, 0xb225000000000000, 0xff0f00000000, // SET SECONDARY ASN (SSAR R1)
+ [8]*argField{ap_Reg_24_27}},
+ {SSAIR, 0xffff000000000000, 0xb99f000000000000, 0xff0f00000000, // SET SECONDARY ASN WITH INSTANCE (SSAIR R1)
+ [8]*argField{ap_Reg_24_27}},
+ {SSKE, 0xffff000000000000, 0xb22b000000000000, 0xf0000000000, // SET STORAGE KEY EXTENDED (SSKE R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {SSM, 0xff00000000000000, 0x8000000000000000, 0x0, // SET SYSTEM MASK (SSM D1(B1))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SRP, 0xff00000000000000, 0xf000000000000000, 0x0, // SHIFT AND ROUND DECIMAL (SRP D1(L1,B1),D2(B2),I3)
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_ImmUnsigned_12_15}},
+ {SLDA, 0xff00000000000000, 0x8f00000000000000, 0xf000000000000, // SHIFT LEFT DOUBLE (64) (SLDA R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SLDL, 0xff00000000000000, 0x8d00000000000000, 0xf000000000000, // SHIFT LEFT DOUBLE LOGICAL (64) (SLDL R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SLA, 0xff00000000000000, 0x8b00000000000000, 0xf000000000000, // SHIFT LEFT SINGLE (32) (SLA R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SLAK, 0xff00000000ff0000, 0xeb00000000dd0000, 0x0, // SHIFT LEFT SINGLE (32) (SLAK R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SLAG, 0xff00000000ff0000, 0xeb000000000b0000, 0x0, // SHIFT LEFT SINGLE (64) (SLAG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SLL, 0xff00000000000000, 0x8900000000000000, 0xf000000000000, // SHIFT LEFT SINGLE LOGICAL (32) (SLL R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SLLK, 0xff00000000ff0000, 0xeb00000000df0000, 0x0, // SHIFT LEFT SINGLE LOGICAL (32) (SLLK R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SLLG, 0xff00000000ff0000, 0xeb000000000d0000, 0x0, // SHIFT LEFT SINGLE LOGICAL (64) (SLLG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SRDA, 0xff00000000000000, 0x8e00000000000000, 0xf000000000000, // SHIFT RIGHT DOUBLE (64) (SRDA R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SRDL, 0xff00000000000000, 0x8c00000000000000, 0xf000000000000, // SHIFT RIGHT DOUBLE LOGICAL (64) (SRDL R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SRA, 0xff00000000000000, 0x8a00000000000000, 0xf000000000000, // SHIFT RIGHT SINGLE (32) (SRA R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SRAK, 0xff00000000ff0000, 0xeb00000000dc0000, 0x0, // SHIFT RIGHT SINGLE (32) (SRAK R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SRAG, 0xff00000000ff0000, 0xeb000000000a0000, 0x0, // SHIFT RIGHT SINGLE (64) (SRAG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SRL, 0xff00000000000000, 0x8800000000000000, 0xf000000000000, // SHIFT RIGHT SINGLE LOGICAL (32) (SRL R1,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SRLK, 0xff00000000ff0000, 0xeb00000000de0000, 0x0, // SHIFT RIGHT SINGLE LOGICAL (32) (SRLK R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SRLG, 0xff00000000ff0000, 0xeb000000000c0000, 0x0, // SHIFT RIGHT SINGLE LOGICAL (64) (SRLG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {SLXT, 0xff00000000ff0000, 0xed00000000480000, 0xf000000, // SHIFT SIGNIFICAND LEFT (extended DFP) (SLXT R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SLDT, 0xff00000000ff0000, 0xed00000000400000, 0xf000000, // SHIFT SIGNIFICAND LEFT (long DFP) (SLDT R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SRXT, 0xff00000000ff0000, 0xed00000000490000, 0xf000000, // SHIFT SIGNIFICAND RIGHT (extended DFP) (SRXT R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SRDT, 0xff00000000ff0000, 0xed00000000410000, 0xf000000, // SHIFT SIGNIFICAND RIGHT (long DFP) (SRDT R1,R3,D2(X2,B2))
+ [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SIGP, 0xff00000000000000, 0xae00000000000000, 0x0, // SIGNAL PROCESSOR (SIGP R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {SORTL, 0xffff000000000000, 0xb938000000000000, 0xff0000000000, // SORT LISTS (SORTL R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SQXBR, 0xffff000000000000, 0xb316000000000000, 0xff0000000000, // SQUARE ROOT (extended BFP) (SQXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SQXR, 0xffff000000000000, 0xb336000000000000, 0xff0000000000, // SQUARE ROOT (extended HFP) (SQXR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SQDB, 0xff00000000ff0000, 0xed00000000150000, 0xff000000, // SQUARE ROOT (long BFP) (SQDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SQDBR, 0xffff000000000000, 0xb315000000000000, 0xff0000000000, // SQUARE ROOT (long BFP) (SQDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SQD, 0xff00000000ff0000, 0xed00000000350000, 0xff000000, // SQUARE ROOT (long HFP) (SQD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SQDR, 0xffff000000000000, 0xb244000000000000, 0xff0000000000, // SQUARE ROOT (long HFP) (SQDR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SQEB, 0xff00000000ff0000, 0xed00000000140000, 0xff000000, // SQUARE ROOT (short BFP) (SQEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SQEBR, 0xffff000000000000, 0xb314000000000000, 0xff0000000000, // SQUARE ROOT (short BFP) (SQEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SQE, 0xff00000000ff0000, 0xed00000000340000, 0xff000000, // SQUARE ROOT (short HFP) (SQE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SQER, 0xffff000000000000, 0xb245000000000000, 0xff0000000000, // SQUARE ROOT (short HFP) (SQER R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SSCH, 0xffff000000000000, 0xb233000000000000, 0x0, // START SUBCHANNEL (SSCH D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {ST, 0xff00000000000000, 0x5000000000000000, 0x0, // STORE (32) (ST R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STY, 0xff00000000ff0000, 0xe300000000500000, 0x0, // STORE (32) (STY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STG, 0xff00000000ff0000, 0xe300000000240000, 0x0, // STORE (64) (STG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STD, 0xff00000000000000, 0x6000000000000000, 0x0, // STORE (long) (STD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STDY, 0xff00000000ff0000, 0xed00000000670000, 0x0, // STORE (long) (STDY R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STE, 0xff00000000000000, 0x7000000000000000, 0x0, // STORE (short) (STE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STEY, 0xff00000000ff0000, 0xed00000000660000, 0x0, // STORE (short) (STEY R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STAM, 0xff00000000000000, 0x9b00000000000000, 0x0, // STORE ACCESS MULTIPLE 7-389 (STAM R1,R3,D2(B2))
+ [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STAMY, 0xff00000000ff0000, 0xeb000000009b0000, 0x0, // STORE ACCESS MULTIPLE 7-389 (STAMY R1,R3,D2(B2))
+ [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {STBEAR, 0xffff000000000000, 0xb201000000000000, 0x0, // STORE BEAR (STBEAR D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCPS, 0xffff000000000000, 0xb23a000000000000, 0x0, // STORE CHANNEL PATH STATUS (STCPS D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCRW, 0xffff000000000000, 0xb239000000000000, 0x0, // STORE CHANNEL REPORT WORD (STCRW D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STC, 0xff00000000000000, 0x4200000000000000, 0x0, // STORE CHARACTER (STC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STCY, 0xff00000000ff0000, 0xe300000000720000, 0x0, // STORE CHARACTER (STCY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STCH, 0xff00000000ff0000, 0xe300000000c30000, 0x0, // STORE CHARACTER HIGH (8) (STCH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STCMH, 0xff00000000ff0000, 0xeb000000002c0000, 0x0, // STORE CHARACTERS UNDER MASK (high) (STCMH R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {STCM, 0xff00000000000000, 0xbe00000000000000, 0x0, // STORE CHARACTERS UNDER MASK (low) (STCM R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCMY, 0xff00000000ff0000, 0xeb000000002d0000, 0x0, // STORE CHARACTERS UNDER MASK (low) (STCMY R1,M3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {STCK, 0xffff000000000000, 0xb205000000000000, 0x0, // STORE CLOCK (STCK D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCKC, 0xffff000000000000, 0xb207000000000000, 0x0, // STORE CLOCK COMPARATOR (STCKC D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCKE, 0xffff000000000000, 0xb278000000000000, 0x0, // STORE CLOCK EXTENDED (STCKE D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCKF, 0xffff000000000000, 0xb27c000000000000, 0x0, // STORE CLOCK FAST (STCKF D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCTL, 0xff00000000000000, 0xb600000000000000, 0x0, // STORE CONTROL (32) (STCTL R1,R3,D2(B2))
+ [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STCTG, 0xff00000000ff0000, 0xeb00000000250000, 0x0, // STORE CONTROL (64) (STCTG R1,R3,D2(B2))
+ [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {STAP, 0xffff000000000000, 0xb212000000000000, 0x0, // STORE CPU ADDRESS (STAP D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STIDP, 0xffff000000000000, 0xb202000000000000, 0x0, // STORE CPU ID (STIDP D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STPT, 0xffff000000000000, 0xb209000000000000, 0x0, // STORE CPU TIMER (STPT D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STFL, 0xffff000000000000, 0xb2b1000000000000, 0x0, // STORE FACILITY LIST (STFL D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STFLE, 0xffff000000000000, 0xb2b0000000000000, 0x0, // STORE FACILITY LIST EXTENDED (STFLE D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STFPC, 0xffff000000000000, 0xb29c000000000000, 0x0, // STORE FPC (STFPC D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STGSC, 0xff00000000ff0000, 0xe300000000490000, 0x0, // STORE GUARDED STORAGE CONTROLS (STGSC R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STH, 0xff00000000000000, 0x4000000000000000, 0x0, // STORE HALFWORD (16) (STH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STHY, 0xff00000000ff0000, 0xe300000000700000, 0x0, // STORE HALFWORD (16) (STHY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STHH, 0xff00000000ff0000, 0xe300000000c70000, 0x0, // STORE HALFWORD HIGH (16) (STHH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STHRL, 0xff0f000000000000, 0xc407000000000000, 0x0, // STORE HALFWORD RELATIVE LONG (16) (STHRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {STFH, 0xff00000000ff0000, 0xe300000000cb0000, 0x0, // STORE HIGH (32) (STFH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STOCFH, 0xff00000000ff0000, 0xeb00000000e10000, 0x0, // STORE HIGH ON CONDITION (STOCFH R1,D2(B2),M3)
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}},
+ {STM, 0xff00000000000000, 0x9000000000000000, 0x0, // STORE MULTIPLE (32) (STM R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STMY, 0xff00000000ff0000, 0xeb00000000900000, 0x0, // STORE MULTIPLE (32) (STMY R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {STMG, 0xff00000000ff0000, 0xeb00000000240000, 0x0, // STORE MULTIPLE (64) (STMG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {STMH, 0xff00000000ff0000, 0xeb00000000260000, 0x0, // STORE MULTIPLE HIGH (32) (STMH R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {STOC, 0xff00000000ff0000, 0xeb00000000f30000, 0x0, // STORE ON CONDITION (32) (STOC R1,D2(B2),M3)
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}},
+ {STOCG, 0xff00000000ff0000, 0xeb00000000e30000, 0x0, // STORE ON CONDITION (64) (STOCG R1,D2(B2),M3)
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}},
+ {STPQ, 0xff00000000ff0000, 0xe3000000008e0000, 0x0, // STORE PAIR TO QUADWORD (STPQ R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STPX, 0xffff000000000000, 0xb211000000000000, 0x0, // STORE PREFIX (STPX D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STRAG, 0xffff000000000000, 0xe502000000000000, 0x0, // STORE REAL ADDRESS (STRAG D1(B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {STRL, 0xff0f000000000000, 0xc40f000000000000, 0x0, // STORE RELATIVE LONG (32) (STRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {STGRL, 0xff0f000000000000, 0xc40b000000000000, 0x0, // STORE RELATIVE LONG (64) (STGRL R1,RI2)
+ [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
+ {STRVH, 0xff00000000ff0000, 0xe3000000003f0000, 0x0, // STORE REVERSED (16) (STRVH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STRV, 0xff00000000ff0000, 0xe3000000003e0000, 0x0, // STORE REVERSED (32) (STRV R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STRVG, 0xff00000000ff0000, 0xe3000000002f0000, 0x0, // STORE REVERSED (64) (STRVG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {STSCH, 0xffff000000000000, 0xb234000000000000, 0x0, // STORE SUBCHANNEL (STSCH D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STSI, 0xffff000000000000, 0xb27d000000000000, 0x0, // STORE SYSTEM INFORMATION (STSI D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {STNSM, 0xff00000000000000, 0xac00000000000000, 0x0, // STORE THEN AND SYSTEM MASK (STNSM D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {STOSM, 0xff00000000000000, 0xad00000000000000, 0x0, // STORE THEN OR SYSTEM MASK (STOSM D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {STURA, 0xffff000000000000, 0xb246000000000000, 0xff0000000000, // STORE USING REAL ADDRESS (32) (STURA R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {STURG, 0xffff000000000000, 0xb925000000000000, 0xff0000000000, // STORE USING REAL ADDRESS (64) (STURG R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {S, 0xff00000000000000, 0x5b00000000000000, 0x0, // SUBTRACT (32) (S R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SR, 0xff00000000000000, 0x1b00000000000000, 0x0, // SUBTRACT (32) (SR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {SRK, 0xffff000000000000, 0xb9f9000000000000, 0xf0000000000, // SUBTRACT (32) (SRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SY, 0xff00000000ff0000, 0xe3000000005b0000, 0x0, // SUBTRACT (32) (SY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SG, 0xff00000000ff0000, 0xe300000000090000, 0x0, // SUBTRACT (64) (SG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SGR, 0xffff000000000000, 0xb909000000000000, 0xff0000000000, // SUBTRACT (64) (SGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SGRK, 0xffff000000000000, 0xb9e9000000000000, 0xf0000000000, // SUBTRACT (64) (SGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SGF, 0xff00000000ff0000, 0xe300000000190000, 0x0, // SUBTRACT (64←32) (SGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SGFR, 0xffff000000000000, 0xb919000000000000, 0xff0000000000, // SUBTRACT (64→32) (SGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SXBR, 0xffff000000000000, 0xb34b000000000000, 0xff0000000000, // SUBTRACT (extended BFP) (SXBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SXTR, 0xffff000000000000, 0xb3db000000000000, 0xf0000000000, // SUBTRACT (extended DFP) (SXTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {SXTRA, 0xffff000000000000, 0xb3db000000000000, 0x0, // SUBTRACT (extended DFP) (SXTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {SDB, 0xff00000000ff0000, 0xed000000001b0000, 0xff000000, // SUBTRACT (long BFP) (SDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SDBR, 0xffff000000000000, 0xb31b000000000000, 0xff0000000000, // SUBTRACT (long BFP) (SDBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SDTR, 0xffff000000000000, 0xb3d3000000000000, 0xf0000000000, // SUBTRACT (long DFP) (SDTR R1,R2,R3)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}},
+ {SDTRA, 0xffff000000000000, 0xb3d3000000000000, 0x0, // SUBTRACT (long DFP) (SDTRA R1,R2,R3,M4)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}},
+ {SEB, 0xff00000000ff0000, 0xed000000000b0000, 0xff000000, // SUBTRACT (short BFP) (SEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SEBR, 0xffff000000000000, 0xb30b000000000000, 0xff0000000000, // SUBTRACT (short BFP) (SEBR R1,R2)
+ [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}},
+ {SP, 0xff00000000000000, 0xfb00000000000000, 0x0, // SUBTRACT DECIMAL (SP D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {SH, 0xff00000000000000, 0x4b00000000000000, 0x0, // SUBTRACT HALFWORD (32←16) (SH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SHY, 0xff00000000ff0000, 0xe3000000007b0000, 0x0, // SUBTRACT HALFWORD (32→16) (SHY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SGH, 0xff00000000ff0000, 0xe300000000390000, 0x0, // SUBTRACT HALFWORD (64→16) (SGH R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SHHHR, 0xffff000000000000, 0xb9c9000000000000, 0xf0000000000, // SUBTRACT HIGH (32) (SHHHR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SHHLR, 0xffff000000000000, 0xb9d9000000000000, 0xf0000000000, // SUBTRACT HIGH (32) (SHHLR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SL, 0xff00000000000000, 0x5f00000000000000, 0x0, // SUBTRACT LOGICAL (32) (SL R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SLR, 0xff00000000000000, 0x1f00000000000000, 0x0, // SUBTRACT LOGICAL (32) (SLR R1,R2)
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15}},
+ {SLRK, 0xffff000000000000, 0xb9fb000000000000, 0xf0000000000, // SUBTRACT LOGICAL (32) (SLRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SLY, 0xff00000000ff0000, 0xe3000000005f0000, 0x0, // SUBTRACT LOGICAL (32) (SLY R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SLG, 0xff00000000ff0000, 0xe3000000000b0000, 0x0, // SUBTRACT LOGICAL (64) (SLG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SLGR, 0xffff000000000000, 0xb90b000000000000, 0xff0000000000, // SUBTRACT LOGICAL (64) (SLGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SLGRK, 0xffff000000000000, 0xb9eb000000000000, 0xf0000000000, // SUBTRACT LOGICAL (64) (SLGRK R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SLGF, 0xff00000000ff0000, 0xe3000000001b0000, 0x0, // SUBTRACT LOGICAL (64←32) (SLGF R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SLGFR, 0xffff000000000000, 0xb91b000000000000, 0xff0000000000, // SUBTRACT LOGICAL (64←32) (SLGFR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SLHHHR, 0xffff000000000000, 0xb9cb000000000000, 0xf0000000000, // SUBTRACT LOGICAL HIGH (32) (SLHHHR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SLHHLR, 0xffff000000000000, 0xb9db000000000000, 0xf0000000000, // SUBTRACT LOGICAL HIGH (32) (SLHHLR R1,R2,R3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
+ {SLFI, 0xff0f000000000000, 0xc205000000000000, 0x0, // SUBTRACT LOGICAL IMMEDIATE (32) (SLFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {SLGFI, 0xff0f000000000000, 0xc204000000000000, 0x0, // SUBTRACT LOGICAL IMMEDIATE (64→32) (SLGFI R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
+ {SLB, 0xff00000000ff0000, 0xe300000000990000, 0x0, // SUBTRACT LOGICAL WITH BORROW (32) (SLB R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SLBR, 0xffff000000000000, 0xb999000000000000, 0xff0000000000, // SUBTRACT LOGICAL WITH BORROW (32) (SLBR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SLBG, 0xff00000000ff0000, 0xe300000000890000, 0x0, // SUBTRACT LOGICAL WITH BORROW (64) (SLBG R1,D2(X2,B2))
+ [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SLBGR, 0xffff000000000000, 0xb989000000000000, 0xff0000000000, // SUBTRACT LOGICAL WITH BORROW (64) (SLBGR R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {SXR, 0xff00000000000000, 0x3700000000000000, 0x0, // SUBTRACT NORMALIZED (extended HFP) (SXR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {SD, 0xff00000000000000, 0x6b00000000000000, 0x0, // SUBTRACT NORMALIZED (long HFP) (SD R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SDR, 0xff00000000000000, 0x2b00000000000000, 0x0, // SUBTRACT NORMALIZED (long HFP) (SDR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {SE, 0xff00000000000000, 0x7b00000000000000, 0x0, // SUBTRACT NORMALIZED (short HFP) (SE R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SER, 0xff00000000000000, 0x3b00000000000000, 0x0, // SUBTRACT NORMALIZED (short HFP) (SER R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {SW, 0xff00000000000000, 0x6f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (long HFP) (SW R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SWR, 0xff00000000000000, 0x2f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (long HFP) (SWR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {SU, 0xff00000000000000, 0x7f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (short HFP) (SU R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {SUR, 0xff00000000000000, 0x3f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (short HFP) (SUR R1,R2)
+ [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}},
+ {SVC, 0xff00000000000000, 0xa00000000000000, 0x0, // SUPERVISOR CALL (SVC I)
+ [8]*argField{ap_ImmUnsigned_8_15}},
+ {TAR, 0xffff000000000000, 0xb24c000000000000, 0xff0000000000, // TEST ACCESS (TAR R1,R2)
+ [8]*argField{ap_ACReg_24_27, ap_Reg_28_31}},
+ {TAM, 0xffff000000000000, 0x10b000000000000, 0x0, // TEST ADDRESSING MODE (TAM)
+ [8]*argField{}},
+ {TS, 0xff00000000000000, 0x9300000000000000, 0x0, // TEST AND SET (TS D1(B1))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {TB, 0xffff000000000000, 0xb22c000000000000, 0xff0000000000, // TEST BLOCK (TB R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {TCXB, 0xff00000000ff0000, 0xed00000000120000, 0xff000000, // TEST DATA CLASS (extended BFP) (TCXB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TDCXT, 0xff00000000ff0000, 0xed00000000580000, 0xff000000, // TEST DATA CLASS (extended DFP) (TDCXT R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TCDB, 0xff00000000ff0000, 0xed00000000110000, 0xff000000, // TEST DATA CLASS (long BFP) (TCDB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TDCDT, 0xff00000000ff0000, 0xed00000000540000, 0xff000000, // TEST DATA CLASS (long DFP) (TDCDT R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TCEB, 0xff00000000ff0000, 0xed00000000100000, 0xff000000, // TEST DATA CLASS (short BFP) (TCEB R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TDCET, 0xff00000000ff0000, 0xed00000000500000, 0xff000000, // TEST DATA CLASS (short DFP) (TDCET R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TDGXT, 0xff00000000ff0000, 0xed00000000590000, 0xff000000, // TEST DATA GROUP (extended DFP) (TDGXT R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TDGDT, 0xff00000000ff0000, 0xed00000000550000, 0xff000000, // TEST DATA GROUP (long DFP) (TDGDT R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TDGET, 0xff00000000ff0000, 0xed00000000510000, 0xff000000, // TEST DATA GROUP (short DFP) (TDGET R1,D2(X2,B2))
+ [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
+ {TP, 0xff00000000ff0000, 0xeb00000000c00000, 0xf0000ff000000, // TEST DECIMAL (TP D1(L1,B1))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19}},
+ {TPEI, 0xffff000000000000, 0xb9a1000000000000, 0xff0000000000, // TEST PENDING EXTERNAL INTERRUPTION (TPEI R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {TPI, 0xffff000000000000, 0xb236000000000000, 0x0, // TEST PENDING INTERRUPTION (TPI D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {TPROT, 0xffff000000000000, 0xe501000000000000, 0x0, // TEST PROTECTION (TPROT D1(B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {TSCH, 0xffff000000000000, 0xb235000000000000, 0x0, // TEST SUBCHANNEL (TSCH D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {TM, 0xff00000000000000, 0x9100000000000000, 0x0, // TEST UNDER MASK (TM D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {TMY, 0xff00000000ff0000, 0xeb00000000510000, 0x0, // TEST UNDER MASK (TMY D1(B1),I2)
+ [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
+ {TMHH, 0xff0f000000000000, 0xa702000000000000, 0x0, // TEST UNDER MASK (high high) (TMHH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {TMHL, 0xff0f000000000000, 0xa703000000000000, 0x0, // TEST UNDER MASK (high low) (TMHL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {TMLH, 0xff0f000000000000, 0xa700000000000000, 0x0, // TEST UNDER MASK (low high) (TMLH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {TMLL, 0xff0f000000000000, 0xa701000000000000, 0x0, // TEST UNDER MASK (low low) (TMLL R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {TMH, 0xff0f000000000000, 0xa700000000000000, 0x0, // TEST UNDER MASK HIGH (TMH R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {TML, 0xff0f000000000000, 0xa701000000000000, 0x0, // TEST UNDER MASK LOW (TML R1,I2)
+ [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
+ {TRACE, 0xff00000000000000, 0x9900000000000000, 0x0, // TRACE (32) (TRACE R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {TRACG, 0xff00000000ff0000, 0xeb000000000f0000, 0x0, // TRACE (64) (TRACG R1,R3,D2(B2))
+ [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}},
+ {TABORT, 0xffff000000000000, 0xb2fc000000000000, 0x0, // TRANSACTION ABORT (TABORT D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {TBEGINC, 0xffff000000000000, 0xe561000000000000, 0x0, // TRANSACTION BEGIN (constrained) (TBEGINC D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}},
+ {TBEGIN, 0xffff000000000000, 0xe560000000000000, 0x0, // TRANSACTION BEGIN (nonconstrained) (TBEGIN D1(B1),I2)
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}},
+ {TEND, 0xffff000000000000, 0xb2f8000000000000, 0xffff00000000, // TRANSACTION END (TEND)
+ [8]*argField{}},
+ {TR, 0xff00000000000000, 0xdc00000000000000, 0x0, // TRANSLATE (TR D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {TRT, 0xff00000000000000, 0xdd00000000000000, 0x0, // TRANSLATE AND TEST (TRT D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {TRTE, 0xffff000000000000, 0xb9bf000000000000, 0xf0000000000, // TRANSLATE AND TEST EXTENDED (TRTE R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {TRTR, 0xff00000000000000, 0xd000000000000000, 0x0, // TRANSLATE AND TEST REVERSE (TRTR D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {TRTRE, 0xffff000000000000, 0xb9bd000000000000, 0xf0000000000, // TRANSLATE AND TEST REVERSE EXTENDED (TRTRE R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {TRE, 0xffff000000000000, 0xb2a5000000000000, 0xff0000000000, // TRANSLATE EXTENDED (TRE R1,R2)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
+ {TROO, 0xffff000000000000, 0xb993000000000000, 0xf0000000000, // TRANSLATE ONE TO ONE (TROO R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {TROT, 0xffff000000000000, 0xb992000000000000, 0xf0000000000, // TRANSLATE ONE TO TWO (TROT R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {TRTO, 0xffff000000000000, 0xb991000000000000, 0xf0000000000, // TRANSLATE TWO TO ONE (TRTO R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {TRTT, 0xffff000000000000, 0xb990000000000000, 0xf0000000000, // TRANSLATE TWO TO TWO (TRTT R1,R2,M3)
+ [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
+ {TRAP2, 0xffff000000000000, 0x1ff000000000000, 0x0, // TRAP (TRAP2)
+ [8]*argField{}},
+ {TRAP4, 0xffff000000000000, 0xb2ff000000000000, 0x0, // TRAP (TRAP4 D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}},
+ {UNPK, 0xff00000000000000, 0xf300000000000000, 0x0, // UNPACK (UNPK D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+ {UNPKA, 0xff00000000000000, 0xea00000000000000, 0x0, // UNPACK ASCII (UNPKA D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {UNPKU, 0xff00000000000000, 0xe200000000000000, 0x0, // UNPACK UNICODE (UNPKU D1(L1,B1),D2(B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
+ {UPT, 0xffff000000000000, 0x102000000000000, 0x0, // UPDATE TREE (UPT)
+ [8]*argField{}},
+ {VA, 0xff00000000ff0000, 0xe700000000f30000, 0xfff00000000, // VECTOR ADD (VA V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VACC, 0xff00000000ff0000, 0xe700000000f10000, 0xfff00000000, // VECTOR ADD COMPUTE CARRY (VACC V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VAP, 0xff00000000ff0000, 0xe600000000710000, 0xf0000000000, // VECTOR ADD DECIMAL (VAP V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VAC, 0xff00000000ff0000, 0xe700000000bb0000, 0xff00000000, // VECTOR ADD WITH CARRY (VAC V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VACCC, 0xff00000000ff0000, 0xe700000000b90000, 0xff00000000, // VECTOR ADD WITH CARRY COMPUTE CARRY (VACCC V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VN, 0xff00000000ff0000, 0xe700000000680000, 0xffff0000000, // VECTOR AND (VN V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VNC, 0xff00000000ff0000, 0xe700000000690000, 0xffff0000000, // VECTOR AND WITH COMPLEMENT (VNC V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VAVG, 0xff00000000ff0000, 0xe700000000f20000, 0xfff00000000, // VECTOR AVERAGE (VAVG V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VAVGL, 0xff00000000ff0000, 0xe700000000f00000, 0xfff00000000, // VECTOR AVERAGE LOGICAL (VAVGL V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VBPERM, 0xff00000000ff0000, 0xe700000000850000, 0xffff0000000, // VECTOR BIT PERMUTE (VBPERM V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VCKSM, 0xff00000000ff0000, 0xe700000000660000, 0xffff0000000, // VECTOR CHECKSUM (VCKSM V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VCP, 0xff00000000ff0000, 0xe600000000770000, 0xf00f0ff0000000, // VECTOR COMPARE DECIMAL (VCP V1,V2,M3)
+ [8]*argField{ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCEQ, 0xff00000000ff0000, 0xe700000000f80000, 0xf0f00000000, // VECTOR COMPARE EQUAL (VCEQ V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCH, 0xff00000000ff0000, 0xe700000000fb0000, 0xf0f00000000, // VECTOR COMPARE HIGH (VCH V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCHL, 0xff00000000ff0000, 0xe700000000f90000, 0xf0f00000000, // VECTOR COMPARE HIGH LOGICAL (VCHL V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCSPH, 0xff00000000ff0000, 0xe6000000007d0000, 0xf0ff0000000, // VECTOR CONVERT HFP TO SCALED DECIMAL (VCSPH V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCVB, 0xff00000000ff0000, 0xe600000000500000, 0xff00f0000000, // VECTOR CONVERT TO BINARY (VCVB R1,V2,M3,M4)
+ [8]*argField{ap_Reg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VCVBG, 0xff00000000ff0000, 0xe600000000520000, 0xff00f0000000, // VECTOR CONVERT TO BINARY (VCVBG R1,V2,M3,M4)
+ [8]*argField{ap_Reg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VCVD, 0xff00000000ff0000, 0xe600000000580000, 0xff0000000000, // VECTOR CONVERT TO DECIMAL (VCVD V1,R2,I3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCVDG, 0xff00000000ff0000, 0xe6000000005a0000, 0xff0000000000, // VECTOR CONVERT TO DECIMAL (VCVDG V1,R2,I3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCLZDP, 0xff00000000ff0000, 0xe600000000510000, 0xff0ff0000000, // VECTOR COUNT LEADING ZERO DIGITS (VCLZDP V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCLZ, 0xff00000000ff0000, 0xe700000000530000, 0xffff00000000, // VECTOR COUNT LEADING ZEROS (VCLZ V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VCTZ, 0xff00000000ff0000, 0xe700000000520000, 0xffff00000000, // VECTOR COUNT TRAILING ZEROS (VCTZ V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VDP, 0xff00000000ff0000, 0xe6000000007a0000, 0xf0000000000, // VECTOR DIVIDE DECIMAL (VDP V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VEC, 0xff00000000ff0000, 0xe700000000db0000, 0xffff00000000, // VECTOR ELEMENT COMPARE (VEC V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VECL, 0xff00000000ff0000, 0xe700000000d90000, 0xffff00000000, // VECTOR ELEMENT COMPARE LOGICAL (VECL V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VERIM, 0xff00000000ff0000, 0xe700000000720000, 0xf0000000000, // VECTORELEMENTROTATEANDINSERTUNDER MASK (VERIM V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VERLL, 0xff00000000ff0000, 0xe700000000330000, 0x0, // VECTOR ELEMENT ROTATE LEFT LOGICAL (VERLL V1,V3,D2(B2),M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VERLLV, 0xff00000000ff0000, 0xe700000000730000, 0xfff00000000, // VECTOR ELEMENT ROTATE LEFT LOGICAL (VERLLV V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VESLV, 0xff00000000ff0000, 0xe700000000700000, 0xfff00000000, // VECTOR ELEMENT SHIFT LEFT (VESLV V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VESL, 0xff00000000ff0000, 0xe700000000300000, 0x0, // VECTOR ELEMENT SHIFT LEFT (VESL V1,V3,D2(B2),M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VESRA, 0xff00000000ff0000, 0xe7000000003a0000, 0x0, // VECTOR ELEMENT SHIFT RIGHT ARITHMETIC (VESRA V1,V3,D2(B2),M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VESRAV, 0xff00000000ff0000, 0xe7000000007a0000, 0xfff00000000, // VECTOR ELEMENT SHIFT RIGHT ARITHMETIC (VESRAV V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VESRL, 0xff00000000ff0000, 0xe700000000380000, 0x0, // VECTOR ELEMENT SHIFT RIGHT LOGICAL (VESRL V1,V3,D2(B2),M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VESRLV, 0xff00000000ff0000, 0xe700000000780000, 0xfff00000000, // VECTOR ELEMENT SHIFT RIGHT LOGICAL (VESRLV V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VX, 0xff00000000ff0000, 0xe7000000006d0000, 0xffff0000000, // VECTOR EXCLUSIVE OR (VX V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VFAE, 0xff00000000ff0000, 0xe700000000820000, 0xf0f00000000, // VECTOR FIND ANY ELEMENT EQUAL (VFAE V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFEE, 0xff00000000ff0000, 0xe700000000800000, 0xf0f00000000, // VECTOR FIND ELEMENT EQUAL (VFEE V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFENE, 0xff00000000ff0000, 0xe700000000810000, 0xf0f00000000, // VECTOR FIND ELEMENT NOT EQUAL (VFENE V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFA, 0xff00000000ff0000, 0xe700000000e30000, 0xff000000000, // VECTOR FP ADD (VFA V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {WFK, 0xff00000000ff0000, 0xe700000000ca0000, 0xfff000000000, // VECTOR FP COMPARE AND SIGNAL SCALAR (WFK V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VFCE, 0xff00000000ff0000, 0xe700000000e80000, 0xf0000000000, // VECTOR FP COMPARE EQUAL (VFCE V1,V2,V3,M4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFCH, 0xff00000000ff0000, 0xe700000000eb0000, 0xf0000000000, // VECTOR FP COMPARE HIGH (VFCH V1,V2,V3,M4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFCHE, 0xff00000000ff0000, 0xe700000000ea0000, 0xf0000000000, // VECTOR FP COMPARE HIGH OR EQUAL (VFCHE V1,V2,V3,M4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {WFC, 0xff00000000ff0000, 0xe700000000cb0000, 0xfff000000000, // VECTOR FP COMPARE SCALAR (WFC V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VCLFNH, 0xff00000000ff0000, 0xe600000000560000, 0xfff000000000, // VECTOR FP CONVERT AND LENGTHEN FROM NNP HIGH (VCLFNH V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VCLFNL, 0xff00000000ff0000, 0xe6000000005e0000, 0xfff000000000, // VECTOR FP CONVERT AND LENGTHEN FROM NNP LOW (VCLFNL V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VCRNF, 0xff00000000ff0000, 0xe600000000750000, 0xff000000000, // VECTOR FP CONVERT AND ROUND TO NNP (VCRNF V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VCFPS, 0xff00000000ff0000, 0xe700000000c30000, 0xff0000000000, // VECTOR FP CONVERT FROM FIXED (VCFPS V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCDG, 0xff00000000ff0000, 0xe700000000c30000, 0xff0000000000, // VECTOR FP CONVERT FROM FIXED 64-BIT (VCDG V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCFPL, 0xff00000000ff0000, 0xe700000000c10000, 0xff0000000000, // VECTOR FP CONVERT FROM LOGICAL (VCFPL V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCDLG, 0xff00000000ff0000, 0xe700000000c10000, 0xff0000000000, // VECTOR FP CONVERT FROM LOGICAL 64-BIT (VCDLG V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCFN, 0xff00000000ff0000, 0xe6000000005d0000, 0xfff000000000, // VECTOR FP CONVERT FROM NNP (VCFN V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VCSFP, 0xff00000000ff0000, 0xe700000000c20000, 0xff0000000000, // VECTOR FP CONVERT TO FIXED (VCSFP V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCGD, 0xff00000000ff0000, 0xe700000000c20000, 0xff0000000000, // VECTOR FP CONVERT TO FIXED 64-BIT (VCGD V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCLFP, 0xff00000000ff0000, 0xe700000000c00000, 0xff0000000000, // VECTOR FP CONVERT TO LOGICAL (VCLFP V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCLGD, 0xff00000000ff0000, 0xe700000000c00000, 0xff0000000000, // VECTOR FP CONVERT TO LOGICAL 64-BIT (VCLGD V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VCNF, 0xff00000000ff0000, 0xe600000000550000, 0xfff000000000, // VECTOR FP CONVERT TO NNP (VCNF V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VFD, 0xff00000000ff0000, 0xe700000000e50000, 0xff000000000, // VECTOR FP DIVIDE (VFD V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VFLL, 0xff00000000ff0000, 0xe700000000c40000, 0xfff000000000, // VECTOR FP LOAD LENGTHENED (VFLL V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VFLR, 0xff00000000ff0000, 0xe700000000c50000, 0xff0000000000, // VECTOR FP LOAD ROUNDED (VFLR V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFMAX, 0xff00000000ff0000, 0xe700000000ef0000, 0xf0000000000, // VECTOR FP MAXIMUM (VFMAX V1,V2,V3,M4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFMIN, 0xff00000000ff0000, 0xe700000000ee0000, 0xf0000000000, // VECTOR FP MINIMUM (VFMIN V1,V2,V3,M4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFM, 0xff00000000ff0000, 0xe700000000e70000, 0xff000000000, // VECTOR FP MULTIPLY (VFM V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VFMA, 0xff00000000ff0000, 0xe7000000008f0000, 0xf000000000, // VECTOR FP MULTIPLY AND ADD (VFMA V1,V2,V3,V4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VFMS, 0xff00000000ff0000, 0xe7000000008e0000, 0xf000000000, // VECTOR FP MULTIPLY AND SUBTRACT (VFMS V1,V2,V3,V4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VFNMA, 0xff00000000ff0000, 0xe7000000009f0000, 0xf000000000, // VECTOR FP NEGATIVE MULTIPLY AND ADD (VFNMA V1,V2,V3,V4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VFNMS, 0xff00000000ff0000, 0xe7000000009e0000, 0xf000000000, // VECTOR FP NEGATIVE MULTIPLY AND SUBTRACT (VFNMS V1,V2,V3,V4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VFPSO, 0xff00000000ff0000, 0xe700000000cc0000, 0xff0000000000, // VECTOR FP PERFORM SIGN OPERATION (VFPSO V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VFSQ, 0xff00000000ff0000, 0xe700000000ce0000, 0xfff000000000, // VECTOR FP SQUARE ROOT (VFSQ V1,V2,M3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VFS, 0xff00000000ff0000, 0xe700000000e20000, 0xff000000000, // VECTOR FP SUBTRACT (VFS V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VFTCI, 0xff00000000ff0000, 0xe7000000004a0000, 0x0, // VECTOR FP TEST DATA CLASS IMMEDIATE (VFTCI V1,V2,I3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_16_27, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}},
+ {VGFM, 0xff00000000ff0000, 0xe700000000b40000, 0xfff00000000, // VECTOR GALOIS FIELD MULTIPLY SUM (VGFM V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VGFMA, 0xff00000000ff0000, 0xe700000000bc0000, 0xff00000000, // VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE (VGFMA V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VGEF, 0xff00000000ff0000, 0xe700000000130000, 0x0, // VECTOR GATHER ELEMENT (32) (VGEF V1,D2(V2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VGEG, 0xff00000000ff0000, 0xe700000000120000, 0x0, // VECTOR GATHER ELEMENT (64) (VGEG V1,D2(V2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VGBM, 0xff00000000ff0000, 0xe700000000440000, 0xf0000f0000000, // VECTOR GENERATE BYTE MASK (VGBM V1,I2)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_ImmUnsigned_36_39}},
+ {VGM, 0xff00000000ff0000, 0xe700000000460000, 0xf000000000000, // VECTOR GENERATE MASK (VGM V1,I2,I3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VISTR, 0xff00000000ff0000, 0xe7000000005c0000, 0xff0f00000000, // VECTOR ISOLATE STRING (VISTR V1,V2,M3,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VL, 0xff00000000ff0000, 0xe700000000060000, 0x0, // VECTOR LOAD (VL V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLR, 0xff00000000ff0000, 0xe700000000560000, 0xfffff0000000, // VECTOR LOAD (VLR V1,V2)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_36_39}},
+ {VLREP, 0xff00000000ff0000, 0xe700000000050000, 0x0, // VECTOR LOAD AND REPLICATE (VLREP V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEBRH, 0xff00000000ff0000, 0xe600000000010000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT (16) (VLEBRH V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEBRF, 0xff00000000ff0000, 0xe600000000030000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT (32) (VLEBRF V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEBRG, 0xff00000000ff0000, 0xe600000000020000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT (64) (VLEBRG V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLBRREP, 0xff00000000ff0000, 0xe600000000050000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLLEBRZ, 0xff00000000ff0000, 0xe600000000040000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLBR, 0xff00000000ff0000, 0xe600000000060000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLC, 0xff00000000ff0000, 0xe700000000de0000, 0xffff00000000, // VECTOR LOAD COMPLEMENT (VLC V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEH, 0xff00000000ff0000, 0xe700000000010000, 0x0, // VECTOR LOAD ELEMENT (16) (VLEH V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEF, 0xff00000000ff0000, 0xe700000000030000, 0x0, // VECTOR LOAD ELEMENT (32) (VLEF V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEG, 0xff00000000ff0000, 0xe700000000020000, 0x0, // VECTOR LOAD ELEMENT (64) (VLEG V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEB, 0xff00000000ff0000, 0xe700000000000000, 0x0, // VECTOR LOAD ELEMENT (8) (VLEB V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEIH, 0xff00000000ff0000, 0xe700000000410000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (16) (VLEIH V1,I2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEIF, 0xff00000000ff0000, 0xe700000000430000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (32) (VLEIF V1,I2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEIG, 0xff00000000ff0000, 0xe700000000420000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (64) (VLEIG V1,I2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLEIB, 0xff00000000ff0000, 0xe700000000400000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (8) (VLEIB V1,I2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLER, 0xff00000000ff0000, 0xe600000000070000, 0x0, // VECTOR LOAD ELEMENTS REVERSED (VLER V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VFI, 0xff00000000ff0000, 0xe700000000c70000, 0xff0000000000, // VECTOR LOAD FP INTEGER (VFI V1,V2,M3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VLGV, 0xff00000000ff0000, 0xe700000000210000, 0x0, // VECTOR LOAD GR FROM VR ELEMENT (VLGV R1,V3,D2(B2),M4)
+ [8]*argField{ap_Reg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLIP, 0xff00000000ff0000, 0xe600000000490000, 0xf000000000000, // VECTOR LOAD IMMEDIATE DECIMAL (VLIP V1,I2,I3)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_ImmUnsigned_32_35, ap_ImmUnsigned_36_39}},
+ {VLLEZ, 0xff00000000ff0000, 0xe700000000040000, 0x0, // VECTOR LOAD LOGICAL ELEMENT AND ZERO (VLLEZ V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLM, 0xff00000000ff0000, 0xe700000000360000, 0x0, // VECTOR LOAD MULTIPLE (VLM V1,V3,D2(B2),M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLP, 0xff00000000ff0000, 0xe700000000df0000, 0xffff00000000, // VECTOR LOAD POSITIVE (VLP V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLRL, 0xff00000000ff0000, 0xe600000000350000, 0x0, // VECTOR LOAD RIGHTMOST WITH LENGTH (VLRL V1,D2(B2),I3)
+ [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}},
+ {VLRLR, 0xff00000000ff0000, 0xe600000000370000, 0xf0000000000000, // VECTOR LOAD RIGHTMOST WITH LENGTH (VLRLR V1,R3,D2(B2))
+ [8]*argField{ap_VecReg_32_35, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}},
+ {VLBB, 0xff00000000ff0000, 0xe700000000070000, 0x0, // VECTOR LOAD TO BLOCK BOUNDARY (VLBB V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLVG, 0xff00000000ff0000, 0xe700000000220000, 0x0, // VECTOR LOAD VR ELEMENT FROM GR (VLVG V1,R3,D2(B2),M4)
+ [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VLVGP, 0xff00000000ff0000, 0xe700000000620000, 0xffff0000000, // VECTOR LOAD VR FROM GRS DISJOINT (VLVGP V1,R2,R3)
+ [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_Reg_16_19, ap_ImmUnsigned_36_39}},
+ {VLL, 0xff00000000ff0000, 0xe700000000370000, 0xf0000000, // VECTOR LOAD WITH LENGTH (VLL V1,R3,D2(B2))
+ [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}},
+ {VMX, 0xff00000000ff0000, 0xe700000000ff0000, 0xfff00000000, // VECTOR MAXIMUM (VMX V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMXL, 0xff00000000ff0000, 0xe700000000fd0000, 0xfff00000000, // VECTOR MAXIMUM LOGICAL (VMXL V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMRH, 0xff00000000ff0000, 0xe700000000610000, 0xfff00000000, // VECTOR MERGE HIGH (VMRH V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMRL, 0xff00000000ff0000, 0xe700000000600000, 0xfff00000000, // VECTOR MERGE LOW (VMRL V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMN, 0xff00000000ff0000, 0xe700000000fe0000, 0xfff00000000, // VECTOR MINIMUM (VMN V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMNL, 0xff00000000ff0000, 0xe700000000fc0000, 0xfff00000000, // VECTOR MINIMUM LOGICAL (VMNL V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMAE, 0xff00000000ff0000, 0xe700000000ae0000, 0xff00000000, // VECTOR MULTIPLY AND ADD EVEN (VMAE V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VMAH, 0xff00000000ff0000, 0xe700000000ab0000, 0xff00000000, // VECTOR MULTIPLY AND ADD HIGH (VMAH V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VMALE, 0xff00000000ff0000, 0xe700000000ac0000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOGICAL EVEN (VMALE V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VMALH, 0xff00000000ff0000, 0xe700000000a90000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOGICAL HIGH (VMALH V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VMALO, 0xff00000000ff0000, 0xe700000000ad0000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOGICAL ODD (VMALO V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VMAL, 0xff00000000ff0000, 0xe700000000aa0000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOW (VMAL V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VMAO, 0xff00000000ff0000, 0xe700000000af0000, 0xff00000000, // VECTOR MULTIPLY AND ADD ODD (VMAO V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VMSP, 0xff00000000ff0000, 0xe600000000790000, 0xf0000000000, // VECTOR MULTIPLY AND SHIFT DECIMAL (VMSP V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VMP, 0xff00000000ff0000, 0xe600000000780000, 0xf0000000000, // VECTOR MULTIPLY DECIMAL (VMP V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VME, 0xff00000000ff0000, 0xe700000000a60000, 0xfff00000000, // VECTOR MULTIPLY EVEN (VME V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMH, 0xff00000000ff0000, 0xe700000000a30000, 0xfff00000000, // VECTOR MULTIPLY HIGH (VMH V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMLE, 0xff00000000ff0000, 0xe700000000a40000, 0xfff00000000, // VECTOR MULTIPLY LOGICAL EVEN (VMLE V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMLH, 0xff00000000ff0000, 0xe700000000a10000, 0xfff00000000, // VECTOR MULTIPLY LOGICAL HIGH (VMLH V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMLO, 0xff00000000ff0000, 0xe700000000a50000, 0xfff00000000, // VECTOR MULTIPLY LOGICAL ODD (VMLO V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VML, 0xff00000000ff0000, 0xe700000000a20000, 0xfff00000000, // VECTOR MULTIPLY LOW (VML V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMO, 0xff00000000ff0000, 0xe700000000a70000, 0xfff00000000, // VECTOR MULTIPLY ODD (VMO V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VMSL, 0xff00000000ff0000, 0xe700000000b80000, 0xf00000000, // VECTOR MULTIPLY SUM LOGICAL (VMSL V1,V2,V3,V4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VNN, 0xff00000000ff0000, 0xe7000000006e0000, 0xffff0000000, // VECTOR NAND (VNN V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VNO, 0xff00000000ff0000, 0xe7000000006b0000, 0xffff0000000, // VECTOR NOR (VNO V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VNX, 0xff00000000ff0000, 0xe7000000006c0000, 0xffff0000000, // VECTOR NOT EXCLUSIVE OR (VNX V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VO, 0xff00000000ff0000, 0xe7000000006a0000, 0xffff0000000, // VECTOR OR (VO V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VOC, 0xff00000000ff0000, 0xe7000000006f0000, 0xffff0000000, // VECTOR OR WITH COMPLEMENT (VOC V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VPK, 0xff00000000ff0000, 0xe700000000940000, 0xfff00000000, // VECTOR PACK (VPK V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VPKLS, 0xff00000000ff0000, 0xe700000000950000, 0xf0f00000000, // VECTOR PACK LOGICAL SATURATE (VPKLS V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VPKS, 0xff00000000ff0000, 0xe700000000970000, 0xf0f00000000, // VECTOR PACK SATURATE (VPKS V1,V2,V3,M4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VPKZ, 0xff00000000ff0000, 0xe600000000340000, 0x0, // VECTOR PACK ZONED (VPKZ V1,D2(B2),I3)
+ [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}},
+ {VPKZR, 0xff00000000ff0000, 0xe600000000700000, 0xf0000000000, // VECTOR PACK ZONED REGISTER (VPKZR V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VPSOP, 0xff00000000ff0000, 0xe6000000005b0000, 0x0, // VECTOR PERFORM SIGN OPERATION DECIMAL (VPSOP V1,V2,I3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_28_35, ap_ImmUnsigned_16_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VPERM, 0xff00000000ff0000, 0xe7000000008c0000, 0xfff00000000, // VECTOR PERMUTE (VPERM V1,V2,V3,V4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_ImmUnsigned_36_39}},
+ {VPDI, 0xff00000000ff0000, 0xe700000000840000, 0xfff00000000, // VECTOR PERMUTE DOUBLEWORD IMMEDIATE (VPDI V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VPOPCT, 0xff00000000ff0000, 0xe700000000500000, 0xffff00000000, // VECTOR POPULATION COUNT (VPOPCT V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VRP, 0xff00000000ff0000, 0xe6000000007b0000, 0xf0000000000, // VECTOR REMAINDER DECIMAL (VRP V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VREP, 0xff00000000ff0000, 0xe7000000004d0000, 0x0, // VECTOR REPLICATE (VREP V1,V3,I2,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VREPI, 0xff00000000ff0000, 0xe700000000450000, 0xf000000000000, // VECTOR REPLICATE IMMEDIATE (VREPI V1,I2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSCEF, 0xff00000000ff0000, 0xe7000000001b0000, 0x0, // VECTOR SCATTER ELEMENT (32) (VSCEF V1,D2(V2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSCEG, 0xff00000000ff0000, 0xe7000000001a0000, 0x0, // VECTOR SCATTER ELEMENT (64) (VSCEG V1,D2(V2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSEL, 0xff00000000ff0000, 0xe7000000008d0000, 0xfff00000000, // VECTOR SELECT (VSEL V1,V2,V3,V4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_ImmUnsigned_36_39}},
+ {VSDP, 0xff00000000ff0000, 0xe6000000007e0000, 0xf0000000000, // VECTOR SHIFT AND DIVIDE DECIMAL (VSDP V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VSRP, 0xff00000000ff0000, 0xe600000000590000, 0x0, // VECTOR SHIFT AND ROUND DECIMAL (VSRP V1,V2,I3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_28_35, ap_ImmUnsigned_16_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VSRPR, 0xff00000000ff0000, 0xe600000000720000, 0xf0000000000, // VECTOR SHIFT AND ROUND DECIMAL REGISTER (VSRPR V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VSL, 0xff00000000ff0000, 0xe700000000740000, 0xffff0000000, // VECTOR SHIFT LEFT (VSL V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSLB, 0xff00000000ff0000, 0xe700000000750000, 0xffff0000000, // VECTOR SHIFT LEFT BY BYTE (VSLB V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSLD, 0xff00000000ff0000, 0xe700000000860000, 0xf00f0000000, // VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD V1,V2,V3,I4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_ImmUnsigned_36_39}},
+ {VSLDB, 0xff00000000ff0000, 0xe700000000770000, 0xf00f0000000, // VECTOR SHIFT LEFT DOUBLE BY BYTE (VSLDB V1,V2,V3,I4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_ImmUnsigned_36_39}},
+ {VSRA, 0xff00000000ff0000, 0xe7000000007e0000, 0xffff0000000, // VECTOR SHIFT RIGHT ARITHMETIC (VSRA V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSRAB, 0xff00000000ff0000, 0xe7000000007f0000, 0xffff0000000, // VECTOR SHIFT RIGHT ARITHMETIC BY BYTE (VSRAB V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSRD, 0xff00000000ff0000, 0xe700000000870000, 0xf00f0000000, // VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD V1,V2,V3,I4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_ImmUnsigned_36_39}},
+ {VSRL, 0xff00000000ff0000, 0xe7000000007c0000, 0xffff0000000, // VECTOR SHIFT RIGHT LOGICAL (VSRL V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSRLB, 0xff00000000ff0000, 0xe7000000007d0000, 0xffff0000000, // VECTOR SHIFT RIGHT LOGICAL BY BYTE (VSRLB V1,V2,V3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSEG, 0xff00000000ff0000, 0xe7000000005f0000, 0xffff00000000, // VECTOR SIGN EXTEND TO DOUBLEWORD (VSEG V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VST, 0xff00000000ff0000, 0xe7000000000e0000, 0x0, // VECTOR STORE (VST V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTEBRH, 0xff00000000ff0000, 0xe600000000090000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENT(16) (VSTEBRH V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTEBRF, 0xff00000000ff0000, 0xe6000000000b0000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENT(32) (VSTEBRF V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTEBRG, 0xff00000000ff0000, 0xe6000000000a0000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENT(64) (VSTEBRG V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTBR, 0xff00000000ff0000, 0xe6000000000e0000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTEH, 0xff00000000ff0000, 0xe700000000090000, 0x0, // VECTOR STORE ELEMENT (16) (VSTEH V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTEF, 0xff00000000ff0000, 0xe7000000000b0000, 0x0, // VECTOR STORE ELEMENT (32) (VSTEF V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTEG, 0xff00000000ff0000, 0xe7000000000a0000, 0x0, // VECTOR STORE ELEMENT (64) (VSTEG V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTEB, 0xff00000000ff0000, 0xe700000000080000, 0x0, // VECTOR STORE ELEMENT (8) (VSTEB V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTER, 0xff00000000ff0000, 0xe6000000000f0000, 0x0, // VECTOR STORE ELEMENTS REVERSED (VSTER V1,D2(X2,B2),M3)
+ [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTM, 0xff00000000ff0000, 0xe7000000003e0000, 0x0, // VECTOR STORE MULTIPLE (VSTM V1,V3,D2(B2),M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSTRL, 0xff00000000ff0000, 0xe6000000003d0000, 0x0, // VECTOR STORE RIGHTMOST WITH LENGTH (VSTRL V1,D2(B2),I3)
+ [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}},
+ {VSTRLR, 0xff00000000ff0000, 0xe6000000003f0000, 0xf0000000000000, // VECTOR STORE RIGHTMOST WITH LENGTH (VSTRLR V1,R3,D2(B2))
+ [8]*argField{ap_VecReg_32_35, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSTL, 0xff00000000ff0000, 0xe7000000003f0000, 0xf0000000, // VECTOR STORE WITH LENGTH (VSTL V1,R3,D2(B2))
+ [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}},
+ {VSTRC, 0xff00000000ff0000, 0xe7000000008a0000, 0xf00000000, // VECTOR STRING RANGE COMPARE (VSTRC V1,V2,V3,V4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VSTRS, 0xff00000000ff0000, 0xe7000000008b0000, 0xf00000000, // VECTOR STRING SEARCH (VSTRS V1,V2,V3,V4,M5,M6)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VS, 0xff00000000ff0000, 0xe700000000f70000, 0xfff00000000, // VECTOR SUBTRACT (VS V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSCBI, 0xff00000000ff0000, 0xe700000000f50000, 0xfff00000000, // VECTOR SUBTRACT COMPUTE BORROW INDICATION (VSCBI V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSP, 0xff00000000ff0000, 0xe600000000730000, 0xf0000000000, // VECTOR SUBTRACT DECIMAL (VSP V1,V2,V3,I4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VSBCBI, 0xff00000000ff0000, 0xe700000000bd0000, 0xff00000000, // VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION (VSBCBI V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VSBI, 0xff00000000ff0000, 0xe700000000bf0000, 0xff00000000, // VECTOR SUBTRACT WITH BORROW INDICATION (VSBI V1,V2,V3,V4,M5)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}},
+ {VSUMG, 0xff00000000ff0000, 0xe700000000650000, 0xfff00000000, // VECTOR SUM ACROSS DOUBLEWORD (VSUMG V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSUMQ, 0xff00000000ff0000, 0xe700000000670000, 0xfff00000000, // VECTOR SUM ACROSS QUADWORD (VSUMQ V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VSUM, 0xff00000000ff0000, 0xe700000000640000, 0xfff00000000, // VECTOR SUM ACROSS WORD (VSUM V1,V2,V3,M4)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VTP, 0xff00000000ff0000, 0xe6000000005f0000, 0xf0fffff0000000, // VECTOR TEST DECIMAL (VTP V1)
+ [8]*argField{ap_VecReg_12_15, ap_ImmUnsigned_36_39}},
+ {VTM, 0xff00000000ff0000, 0xe700000000d80000, 0xfffff0000000, // VECTOR TEST UNDER MASK (VTM V1,V2)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_36_39}},
+ {VUPH, 0xff00000000ff0000, 0xe700000000d70000, 0xffff00000000, // VECTOR UNPACK HIGH (VUPH V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VUPLH, 0xff00000000ff0000, 0xe700000000d50000, 0xffff00000000, // VECTOR UNPACK LOGICAL HIGH (VUPLH V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VUPLL, 0xff00000000ff0000, 0xe700000000d40000, 0xffff00000000, // VECTOR UNPACK LOGICAL LOW (VUPLL V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VUPL, 0xff00000000ff0000, 0xe700000000d60000, 0xffff00000000, // VECTOR UNPACK LOW (VUPL V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
+ {VUPKZ, 0xff00000000ff0000, 0xe6000000003c0000, 0x0, // VECTOR UNPACK ZONED (VUPKZ V1,D2(B2),I3)
+ [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}},
+ {VUPKZH, 0xff00000000ff0000, 0xe600000000540000, 0xff0ff0000000, // VECTOR UNPACK ZONED HIGH (VUPKZH V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {VUPKZL, 0xff00000000ff0000, 0xe6000000005c0000, 0xff0ff0000000, // VECTOR UNPACK ZONED LOW (VUPKZL V1,V2,M3)
+ [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_ImmUnsigned_36_39}},
+ {ZAP, 0xff00000000000000, 0xf800000000000000, 0x0, // ZERO AND ADD (ZAP D1(L1,B1),D2(L2,B2))
+ [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}},
+}
diff --git a/src/cmd/vendor/modules.txt b/src/cmd/vendor/modules.txt
index e30941d68b993657fa8ebb7130cf2474a0305a24..c99bc74ce0fd2fa1c659b90e85181be85307be40 100644
--- a/src/cmd/vendor/modules.txt
+++ b/src/cmd/vendor/modules.txt
@@ -16,11 +16,12 @@ github.com/google/pprof/third_party/svgpan
# github.com/ianlancetaylor/demangle v0.0.0-20240312041847-bd984b5ce465
## explicit; go 1.13
github.com/ianlancetaylor/demangle
-# golang.org/x/arch v0.8.1-0.20240716161256-b863392466ea
+# golang.org/x/arch v0.9.1-0.20240807172201-9d90945922a7
## explicit; go 1.18
golang.org/x/arch/arm/armasm
golang.org/x/arch/arm64/arm64asm
golang.org/x/arch/ppc64/ppc64asm
+golang.org/x/arch/s390x/s390xasm
golang.org/x/arch/x86/x86asm
# golang.org/x/build v0.0.0-20240722200705-b9910f320300
## explicit; go 1.21